Mail Archives: pgcc/1999/08/14/23:13:49
> On Sat, Aug 14, 1999 at 06:31:25PM +0200, Jan Hubicka wrote:
> > Isn't that mainly because of memory consumed by your program has decreased
> > when you changed your datastructure? K6 is very sensitive about memory,
> > because it have quite small caches and refills are more costy than on the
> > Intel CPU familly.
>
> If I'm not mistaken, the K6 is advertised to have 32k+32k L1 cache,
> while CPU's by Intel mostly have 16k+16k. So your remark seems to
> imply that these numbers are not comparable?
Don't know. I am getting more problems with cache on AMD.
The instruction cache have lots of predecode information (5 bits as I remember)
and loading of caches seems to cause more stalls. I didn't looked exactly
for the reason, just I've noticed that shortening code/reordering loops
to be cache friendly (reading videoram line by line) makes huge speedups
on K6 while smallers on my Pentium.
I was trying to make extreme cache alignment (64kb) the loss in performance
on AMD was roughly 60% while on pentium 15%.
Maybe something is just worng with my setup, but loading cache line seems
to cause many cycles stall.
I am using 100Mhz memories here while slow ones on Pentium...
Honza
>
> Ronald
--
OK. Lets make a signature file.
+-------------------------------------------------------------------------+
| Jan Hubicka (Jan Hubi\v{c}ka in TeX) hubicka AT freesoft DOT cz |
| Czech free software foundation: http://www.freesoft.cz |
|AA project - the new way for computer graphics - http://www.ta.jcu.cz/aa |
| homepage: http://www.paru.cas.cz/~hubicka/, games koules, Xonix, fast |
| fractal zoomer XaoS, index of Czech GNU/Linux/UN*X documentation etc. |
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