Mail Archives: pgcc/1999/07/07/09:28:20
At 01:22 PM 7/7/99 +0200, Jens-Uwe Rumstich wrote:
>Hi!
>
>> >No, IMHO AMD just added new instructions to 3DNow, not new registers,
>> >therefore no new cpu state was needed.
>> >And the Specs are sadly not available, because the K7 is only shipped
>> >to OEMs and not available in stores to the end user :-(
>>
>> K7 is fast and cheap. a real winner. It's nearly as fast as the
>> Xeon at same speed
>
>Its faster than a Xeon at the same speed. The only advantage of the Xeon
>is its proven stability and the availability of 4way SMP-Boards. Once
>these boards are available for the K7 too, it should be better here too
>because the K7 should scale much better.
I'm also looking forward to a motherboard that supports 4 or 8 K7s.
Considering its expected selling prize, and the fact that we finally
get competition for the Xeon now, this really will be a big step forward!
For the program crafty (crafty is in some official benchmarks by
the way, so it makes sense to test it; the command 'bench'
gives you after a few minutes a benchmark in crafty; ftp ftp.cis.uab.edu
for crafty. linux versions of crafty are compiled using pgcc) that
was tested at it, it was not faster than
the Xeon where it normally runs at, at the internet.
K7 was a few % slower, but marginally and the fact that the
only Xeon where we can compare speed with is a quad xeon (so
a benchmark done at it can use the FULL speed of 1 processor)
and the K7 was at a single cpu motherboard,
this might already make the small difference.
It was according to the AMD-man, an experimental K7 at
550Mhz and L2 cache at processor speed (512kb).
>> It seems to me that no new instructions are added to it, but
>There were new instructions added to the 3DNow instruction set. It
>also includes new instructons for Cache prefetching and some DSP-stuff.
>Sadly there is not more know today. You might want to download the speech
>of Dirk Meyer from one of the places mentioned at
Yes apologies i wasn't 100% correct. For something called 3dnow
there are indeed some new instructions, but as compilers don't
use them very well this is of no use for 99% of the programmers.
I can sell a program which runs at all m$ computers, and not a program
which runs only at K7, secondly i'm not gonna write assembler (guess
why i am at this list!).
Assumption is that those instructions which are now useless to me (as i'm
using msvc 6.0 entreprise for commercial releases and for internal
testing and for some quads: pgcc, gcc, egcs, and internal intel compiler)
will get integrated in the CPU as working at the normal
registers.
See specs Merced, note that merced has quite some
registers; work to do for the compilerfreaks!
When compiling my program for some RISC processors i get the impression
registers don't get used very smartly (gcc for the alpha
at an alpha 633Mhz 21164 performs only like a 380Mhz PII for me,
and gcc at a 300Mhz ultrasparc(3d) only performs as a pentium pro200 for me,
So i guess compilers
not using the major part of the merced
registers will be commercial suicide!
>http://www.jc-news.com/pc/article.cgi?AMD/Curtain_Call_K7-01
>> Also unknown is in how far it's 64 bits
>
>Its a normal 32bit cpu.
Thanks!
8 bits programs and 16 bits programs
are way faster at AMD K6 processors than 32 bits programs (see
k6 manuals for the technical explanation for this).
Personally that was a big bummer for me. Speed difference at
K6 was really great; for me a K6 is measurable slower than the
PII at the same Mhz.
However: K6-3 at 600Mhz performed at the world championships
for an assembler program Rebel 2 times faster than a PII-450.
Question: are 32 bits instructions at K7 a lot slower
than 8 bits instructions?
>> For me the K7 at 550Mhz was a big surprise (L2 cache at processor speed,
>> and 512kb of it).
>The level2 cache runs only at half the speed of the CPU, just like the
>cache on P2/P3 machines.
AMD says they release different versions of K7, with cache running at
processor speed, cache at 1/2 and for the 1Ghz versions some did
they reported cache ran at 1/3.
Test i am talking about (integer oriented)
was done at an experimental K7 at 550Mhz running at processor speed,
so i have no option but to believe them on that!
Considering the huge L1 cache (128 kb) of the K7 i wonder how fast
my own program at the K7 is.
>cu
> Jens-Uwe
The new alpha chip 21264
at 500Mhz 21264 was for Ernst A. Heinz (his program is 64 bits)
about 10% faster than the 21164 at 767Mhz.
Now 21164 is a lot slower than PII architecture,
so this means that K7 is a really good for the competition,
because who can afford quad Xeon or dual processor 21264 alpha's?
Now let's sit and wait for the prizes of the K7 quad and octo
boards...
Greetings,
Vincent
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