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From: "Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
Date: Wed, 18 Jan 2017 10:11:35 +0000
Message-ID: <CAJXU7q-8_Reh8evmpD4uJkmDShbDdOZu=cQ3dsupvjdDonoerA@mail.gmail.com>
Subject: Re: [geda-user] [pcb] why no clearpoly on silk
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I'm not sure it makes much sense to treat it differently, but historically
it has been. It's not like your clearing a conductive plane object with
conductive tracks - so I can sort of understand the distinction.

I'm not sure that the element syntax allows any clearance data in the old
pcb file format, so only stuff drawn directly on the design layer would be
affected.

When the clipper code was introduced it changed behaviours, such
introducing the "full poly" flag, which when added mostly restored the old
geometry you'd get from ancient pcb versions without the clipper.  This is
all long in the past, but at the time created problems where older designs
opened with different connectivity in newer pcb.

Given the abundance of existing designs, you might cause silk layer
breakage if you suddenly enable clipping there... unless we also special
cased turning off the flags enabling clearance when drawing / moving new
lines on the silk layers?

Peter

On 18 Jan 2017 07:11, <gedau AT igor2 DOT repo DOT hu> wrote:

> Hi all,
>
> sligtly related to the disappearing silk poly: we do not let polygon
> clearance happen on silk. It's disabled even if both clearline and
> clearpoly are set. Does anyone remember what was the reason for this? Is it
> only that it "doesn't seem practical"? If so, why don't we just let the
> user control this with those flags we already have?
>
> (The relation is that the bug can not be reproduced if the clearpoly flag
> is not set on the silk poly.)
>
> I'm asking this because I am planning to remove this limitation in pcb-rnd
> and let users do clearpoly in whatever layer they want to.
>
> Regards,
>
> Igor2
>

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<div dir=3D"auto">I&#39;m not sure it makes much sense to treat it differen=
tly, but historically it has been. It&#39;s not like your clearing a conduc=
tive plane object with conductive tracks - so I can sort of understand the =
distinction.<div dir=3D"auto"><br></div><div dir=3D"auto">I&#39;m not sure =
that the element syntax allows any clearance data in the old pcb file forma=
t, so only stuff drawn directly on the design layer would be affected.<br><=
div dir=3D"auto"><div dir=3D"auto"><br></div><div dir=3D"auto">When the cli=
pper code was introduced it changed behaviours, such introducing the &quot;=
full poly&quot; flag, which when added mostly restored the old geometry you=
&#39;d get from ancient pcb versions without the clipper.=C2=A0 This is all=
 long in the past, but at the time created problems where older designs ope=
ned with different connectivity in newer pcb.</div><div dir=3D"auto"><br></=
div><div dir=3D"auto">Given the abundance of existing designs, you might ca=
use silk layer breakage if you suddenly enable clipping there... unless we =
also special cased turning off the flags enabling clearance when drawing / =
moving new lines on the silk layers?</div><div dir=3D"auto"><br></div><div =
dir=3D"auto">Peter</div></div></div></div><div class=3D"gmail_extra"><br><d=
iv class=3D"gmail_quote">On 18 Jan 2017 07:11,  &lt;<a href=3D"mailto:gedau=
@igor2.repo.hu">gedau AT igor2 DOT repo DOT hu</a>&gt; wrote:<br type=3D"attribution">=
<blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1p=
x #ccc solid;padding-left:1ex">Hi all,<br>
<br>
sligtly related to the disappearing silk poly: we do not let polygon cleara=
nce happen on silk. It&#39;s disabled even if both clearline and clearpoly =
are set. Does anyone remember what was the reason for this? Is it only that=
 it &quot;doesn&#39;t seem practical&quot;? If so, why don&#39;t we just le=
t the user control this with those flags we already have?<br>
<br>
(The relation is that the bug can not be reproduced if the clearpoly flag i=
s not set on the silk poly.)<br>
<br>
I&#39;m asking this because I am planning to remove this limitation in pcb-=
rnd and let users do clearpoly in whatever layer they want to.<br>
<br>
Regards,<br>
<br>
Igor2<br>
</blockquote></div></div>

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