Mail Archives: geda-user/2016/08/02/16:03:13
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On Tue, Aug 2, 2016 at 11:56 AM, John Doty <jpd AT noqsi DOT com> wrote:
>
> On Aug 2, 2016, at 2:18 PM, Ouabache Designworks (z3qmtr45 AT gmail DOT com)
> [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:
>
>
>
> On Tue, Aug 2, 2016 at 10:27 AM, John Doty <jpd AT noqsi DOT com> wrote:
>
>>
>> On Aug 2, 2016, at 11:55 AM, Ouabache Designworks (z3qmtr45 AT gmail DOT com)
>> [via geda-user AT delorie DOT com] <geda-user AT delorie DOT com> wrote:
>>
>> This group has shown almost no interest in features that are needed by I=
C
>> designers if they are not also needed by PCB designers.
>>
>>
>> What do you imagine IC designers need? I design mixed-signal ASICs in
>> gschem, and do not perceive any limits. Just another application for a
>> complete, general purpose network topology editor.
>>
>> John Doty Noqsi Aerospace, Ltd.
>> http://www.noqsi.com/
>> jpd AT noqsi DOT com
>>
>>
>> How about libraries that you can download that don't have naming
> collisions with other libraries?
>
>
> Since you have complete control of your library path, why is this a
> problem? Just put together the library *your* project needs. No big deal.
> Certainly not something that requires a new *feature*.
>
>
So I need part A from Library foo and part B from library bar when both
libs have both parts. How do I set up the search path?
>
> How about complete hierarchical design support with uniquification?
>
>
> I=E2=80=99m not sure what your problem is. My ASICs are hierarchical (of =
course).
>
When I descend down into a component instance then I want to see the
schematic using all the elaborated values instead of the attribute names.
>
>
> How about Busses? IC's need support for wires,vectors and busses. Gschem
> does wires with some graphic support for vectors but nothing for busses.
>
>
> Need? Maybe they would be nice, but I haven=E2=80=99t really missed them.=
Mostly
> you want them in complex digital parts, I think. If that was the kind of
> chip I was doing, I=E2=80=99d do those straight in HDL, not draw them in =
gschem. In
> any case, there=E2=80=99s nothing preventing you giving a net a name that=
describes
> a bus, and dealing with that downstream.
>
>
Wires and vectors have inputs and outputs. Busses have masters and slaves.
You need to support bundling wires,vectors and busses into bigger busses,
passing it up and down hierarchies and then splitting everything back apart
at the end.
Even if you do hdl you still want to do your top levels in schematics
because that is your documentation and will be in sync with
the design.
>
> Gschem supports small data designs. IC designers need support for big dat=
a
> projects.
>
>
> Big data designs are sanely composed of small data components. Gschem
> handles those small data components well. Drawings don=E2=80=99t scale we=
ll to big
> data, so gschem isn=E2=80=99t the right tool for the higher levels (which=
are more
> like programming than graphical design).
>
>
We used to design ICs using schematic capture until verilog came along.
Then the architects switched from using schematics to Microsoft Visio. It
was a giant step backwards.
>
>
> John Eaton
>
>
>
>
>
>
> John Doty Noqsi Aerospace, Ltd.
>
> http://www.noqsi.com/
>
> jpd AT noqsi DOT com
>
>
>
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<div dir=3D"ltr"><br><div class=3D"gmail_extra"><br><div class=3D"gmail_quo=
te">On Tue, Aug 2, 2016 at 11:56 AM, John Doty <span dir=3D"ltr"><<a hre=
f=3D"mailto:jpd AT noqsi DOT com" target=3D"_blank">jpd AT noqsi DOT com</a>></span> w=
rote:<br><blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;borde=
r-left:1px #ccc solid;padding-left:1ex"><div style=3D"word-wrap:break-word"=
><br><div><span class=3D""><div>On Aug 2, 2016, at 2:18 PM, Ouabache Design=
works (<a href=3D"mailto:z3qmtr45 AT gmail DOT com" target=3D"_blank">z3qmtr45 AT gma=
il.com</a>) [via <a href=3D"mailto:geda-user AT delorie DOT com" target=3D"_blank"=
>geda-user AT delorie DOT com</a>] <<a href=3D"mailto:geda-user AT delorie DOT com" ta=
rget=3D"_blank">geda-user AT delorie DOT com</a>> wrote:</div><br><blockquote t=
ype=3D"cite"><div dir=3D"ltr"><br><div class=3D"gmail_extra"><br><div class=
=3D"gmail_quote">On Tue, Aug 2, 2016 at 10:27 AM, John Doty <span dir=3D"lt=
r"><<a href=3D"mailto:jpd AT noqsi DOT com" target=3D"_blank">jpd AT noqsi DOT com</a>=
></span> wrote:<br><blockquote class=3D"gmail_quote" style=3D"margin:0 0=
0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style=3D"word-wra=
p:break-word"><span><br><div><div>On Aug 2, 2016, at 11:55 AM, Ouabache Des=
ignworks (<a href=3D"mailto:z3qmtr45 AT gmail DOT com" target=3D"_blank">z3qmtr45@=
gmail.com</a>) [via <a href=3D"mailto:geda-user AT delorie DOT com" target=3D"_bla=
nk">geda-user AT delorie DOT com</a>] <<a href=3D"mailto:geda-user AT delorie DOT com"=
target=3D"_blank">geda-user AT delorie DOT com</a>> wrote:</div><br><blockquot=
e type=3D"cite"><span style=3D"font-family:Helvetica;font-size:12px;font-st=
yle:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;lin=
e-height:normal;text-align:start;text-indent:0px;text-transform:none;white-=
space:normal;word-spacing:0px;float:none;display:inline!important">This gro=
up has shown almost no interest in features that are needed by IC designers=
if they are not also needed by PCB designers.</span><br style=3D"font-fami=
ly:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weig=
ht:normal;letter-spacing:normal;line-height:normal;text-align:start;text-in=
dent:0px;text-transform:none;white-space:normal;word-spacing:0px"></blockqu=
ote><br></div></span><div>What do you imagine IC designers need? I design m=
ixed-signal ASICs in gschem, and do not perceive any limits. Just another a=
pplication for a complete, general purpose network topology editor.</div><b=
r><div>
<span style=3D"border-collapse:separate;border-spacing:0px;font-family:Helv=
etica;font-size:12px;font-style:normal;font-variant:normal;font-weight:norm=
al;letter-spacing:normal;line-height:normal;text-indent:0px;text-transform:=
none;white-space:normal;word-spacing:0px"><div style=3D"margin:0px"><font s=
tyle=3D"font:12.0px Helvetica" face=3D"Helvetica" size=3D"3">John Doty<span=
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0<span>=C2=A0</span><span>=C2=A0 =C2=A0<s=
pan>=C2=A0</span></span></span>Noqsi Aerospace, Ltd.</font></div><div style=
=3D"margin:0px"><a href=3D"http://www.noqsi.com/" target=3D"_blank">http://=
www.noqsi.com/</a></div><div style=3D"margin:0px"><font style=3D"font:12.0p=
x Helvetica" face=3D"Helvetica" size=3D"3"><a href=3D"mailto:jpd AT noqsi DOT com"=
target=3D"_blank">jpd AT noqsi DOT com</a></font></div><br></span>
</div>
<br></div></blockquote></div>How about libraries that you can download that=
don't have naming collisions with other libraries?<br></div></div></bl=
ockquote><div><br></div></span>Since you have complete control of your libr=
ary path, why is this a problem? Just put together the library *your* proje=
ct needs. No big deal. Certainly not something that requires a new *feature=
*.</div><div><span class=3D""><br></span></div></div></blockquote><div><br>=
</div><div>So I need part A from Library foo and part B from library bar wh=
en both libs have both parts. How do I set up the search path?<br></div><di=
v><br>=C2=A0</div><blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .=
8ex;border-left:1px #ccc solid;padding-left:1ex"><div style=3D"word-wrap:br=
eak-word"><div><span class=3D""><blockquote type=3D"cite"><div dir=3D"ltr">=
<div class=3D"gmail_extra"><br></div><div class=3D"gmail_extra">How about c=
omplete hierarchical design support with uniquification?<br></div></div></b=
lockquote><div><br></div></span>I=E2=80=99m not sure what your problem is. =
My ASICs are hierarchical (of course).</div></div></blockquote><div><br></d=
iv><div>When I descend down into a component instance then I want to see th=
e schematic using all the elaborated values instead of the attribute names.=
<br></div><div><br>=C2=A0</div><blockquote class=3D"gmail_quote" style=3D"m=
argin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style=3D=
"word-wrap:break-word"><div><span class=3D""><br><blockquote type=3D"cite">=
<div dir=3D"ltr"><div class=3D"gmail_extra"><br></div><div class=3D"gmail_e=
xtra">How about Busses? IC's need support for wires,vectors and busses.=
Gschem does wires with some graphic support for vectors but nothing for bu=
sses.<br></div></div></blockquote><div><br></div></span>Need? Maybe they wo=
uld be nice, but I haven=E2=80=99t really missed them. Mostly you want them=
in complex digital parts, I think. If that was the kind of chip I was doin=
g, I=E2=80=99d do those straight in HDL, not draw them in gschem. In any ca=
se, there=E2=80=99s nothing preventing you giving a net a name that describ=
es a bus, and dealing with that downstream.</div><div><span class=3D""><br>=
</span></div></div></blockquote><div><br><br></div><div>Wires and vectors h=
ave inputs and outputs. Busses have masters and slaves.=C2=A0 You need to s=
upport bundling wires,vectors and busses into bigger busses, passing it up =
and down hierarchies and then splitting everything back apart at the end.<b=
r><br></div><div>Even if you do hdl you still want to do your top levels in=
schematics because that is your documentation and will be in sync with<br>=
</div><div>the design.<br></div><div><br><br>=C2=A0</div><blockquote class=
=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padd=
ing-left:1ex"><div style=3D"word-wrap:break-word"><div><span class=3D""><bl=
ockquote type=3D"cite"><div dir=3D"ltr"><div class=3D"gmail_extra"><br></di=
v><div class=3D"gmail_extra">Gschem supports small data designs. IC designe=
rs need support for big data projects.<br></div></div></blockquote><div><br=
></div></span><div>Big data designs are sanely composed of small data compo=
nents. Gschem handles those small data components well. Drawings don=E2=80=
=99t scale well to big data, so gschem isn=E2=80=99t the right tool for the=
higher levels (which are more like programming than graphical design).</di=
v><br></div></div></blockquote><div><br></div><div>We used to design ICs us=
ing schematic capture until verilog came along. Then the architects switche=
d from using schematics to Microsoft Visio. It was a giant step backwards.<=
br></div><div><br>=C2=A0</div><blockquote class=3D"gmail_quote" style=3D"ma=
rgin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style=3D"=
word-wrap:break-word"><div><blockquote type=3D"cite"><div dir=3D"ltr"><div =
class=3D"gmail_extra"><br><br></div><div class=3D"gmail_extra">John Eaton<b=
r><br></div><div class=3D"gmail_extra"><br></div><div class=3D"gmail_extra"=
><br><br><br></div></div>
</blockquote></div><span class=3D""><br><div>
<span style=3D"border-collapse:separate;border-spacing:0px 0px;color:rgb(0,=
0,0);font-family:Helvetica;font-size:12px;font-style:normal;font-variant:no=
rmal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align=
:auto;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0=
px"><p style=3D"margin:0.0px 0.0px 0.0px 0.0px"><font style=3D"font:12.0px =
Helvetica" face=3D"Helvetica" size=3D"3">John Doty<span>=C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0<span>=C2=A0</span><span>=C2=A0 =C2=A0<span>=C2=A0</span><=
/span></span>Noqsi Aerospace, Ltd.</font></p><p style=3D"margin:0.0px 0.0px=
0.0px 0.0px"><a href=3D"http://www.noqsi.com/" target=3D"_blank">http://ww=
w.noqsi.com/</a></p><p style=3D"margin:0.0px 0.0px 0.0px 0.0px"><font style=
=3D"font:12.0px Helvetica" face=3D"Helvetica" size=3D"3"><a href=3D"mailto:=
jpd AT noqsi DOT com" target=3D"_blank">jpd AT noqsi DOT com</a></font></p><br></span>
</div>
<br></span></div></blockquote></div><br></div></div>
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