Mail Archives: geda-user/2016/02/01/05:31:38
> > Geometry of plating between layers depnend on cut out shape which as
> > is now is a drilled hole and it is no problem to figure out shape of
> > plating on board layer. The other direction to draw cut out on board
> > layer and plating between layer on separate layer with same mechanical
> > position is not hard to implement but require drawing primitives on
> > board and plating layer to agree.
> >
> >> Why is the inter-layer connectivity a fundamentally different different
> >> idea?
> >
> > Because drawing primitives added to the inter layer conectivity must
> > match board cut out edges.
>
> You still want to model a 3D PCB accurately. But that is not the job of
> the layout program and its core data structures.
In sort of but there are two methods:
1. To model as it look then manufacturing is done.
2. It should be possible to deduce how it should look then manufacturing is done.
Then drill size and between which conductive layer hole or cut out should be made it is possible to deduce a accurate 3D pcb model. Your example below should do the trick together with some knowledge of stack up of course.
> Let me draw an example of how I see a via:
>
> A layout with four copper layers, including a gnd plane on an inner
> layer, and a via with 16mil drill, 10mil annulus on the outer layers
> and 8mil annulus on the inner layers, "+" thermals on the GND plane.
>
>
> Layer{name="Vias", connects=("Top", "Mid", "GND", Bot"), Attributes{conductive, elements="THROUGHHOLES"}}
> Layer{name="Top", connects=("Vias"), Attributes{conductive, elements="COMPONENTSIDE"}}
> Layer{name="Mid", connects=("Vias"), Attributes{conductive, elements="INNER"}}
> Layer{name="GND", connects=("Vias"), Attributes{conductive, elements="INNER", planeclearance=8mil}}
> Layer{name="Bot", connects=("Vias"), Attributes{conductive, elements="SOLDERSIDE"}}
> Layer{name="Top:mask", Attributes{elements="COMPONENTSIDE:mask"}}
> Layer{name="Bot:mask", Attributes{elements="SOLDERSIDE:mask"}}
> Layer{name="milling", Attributes{outline}}
>
> Line{layer="milling", width=1mil, Points{(0,0),(0,1000mil),(1000mil,1000mil),(1000mil,0),(0,0)}}
> Polygon { layer="GND", depth=500, Points{(20mil,20mil), (20mil,990mil), (990mil,990mil), (990mil,20mil)} }
>
> # a unplaced Via library object (no origin=)
> Group {
> name="via:signalrouting",
> Attributes{via="signalrouting"},
> Line {layer="Vias", width=16mil, Points{(0,0)}, }
> Line {layer="Top", width=36mil, depth=100, Points{(0,0)}, }
> Line {layer="Top", width=56mil, depth=-200, Points{(0,0)}, Attributes{thermal="clearance"}, }
> Line {layer="Top:mask", width=42mil, depth=-100, Points{(0,0)}, }
> Line {layer="Mid", width=32mil, depth=100, Points{(0,0)}, }
> Line {layer="Mid", width=48mil, depth=-200, Points{(0,0)}, Attributes{thermal="clearance"}, }
> Line {layer="GND", width=32mil, depth=100, Points{(0,0)}, }
> Line {layer="GND", width=48mil, depth=-200, Points{(0,0)}, Attributes{thermal="clearance"}, }
> Line {layer="Bot", width=36mil, depth=100, Points{(0,0)}, }
> Line {layer="Bot:mask", width=42mil, depth=-100, Points{(0,0)}, }
> }
>
> Group { origin=(x,y),
> Group{ref="via:signalrouting", origin=(0,0)}
> Line {layer="GND", width=8mil, depth=200, Points{(0,-50mil), (0,50mil)}, Attributes{thermal="plus"}, }
> Line {layer="GND", width=8mil, depth=200, Points{(-50mil,0), (50mil,0)}, Attributes{thermal="plus"}, }
> }
>
>
>
>
>
> --
> Stephan
I had time to read your example more careful and could only contribute two meaningful comments:
> Layer{name="Top:mask", Attributes{elements="COMPONENTSIDE:mask"}}
I think the mask and silkscreen if there is one should be referenced to TOP conductive layer instead of COMPONENTSIDE. Reason is multi layer above two layer circuit boards are etched before they are assembled and if mask/silk is referenced to conductive layer file format would allow for embedded component soldered on inner layer before board assembled.
I assume
Line {layer="Vias", width=16mil, depth=200, Points{(0,-50mil), (0,50mil)}, Attributes{thermal="plus"}, }
there line is place on via layer would make a plated slit instead of a round hole?
I did not get what "depth=200" is for.
Regards Nicklas Karlsson
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