Mail Archives: geda-user/2016/01/16/16:20:45
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On Jan 16, 2016, at 12:59 PM, DJ Delorie <dj AT delorie DOT com> wrote:
>=20
>> 1. For netlists flattened by gnetlist, we have a configurable syntax
>> for net renaming before the Scheme stuff gets the data. The bus
>> syntax here will have some difficulty with that.
>=20
> Because of my choice of syntax, or because of some design limitation
> in that part of the code? I'm not tied to the syntax, I know verilog
> has a specific one it needs to use, that I don't mind adopting, but I
> figured it would be neccessary for the backend at some point to pick
> "something" via a callback to choose/enable such expansion.
By default, a net nBL,A[8:2] internal to a subcircuit with refdes A1 =
will get the name A1/nBL,A[8:2] when gnetlist flattens hierarchy. That =
won=92t expand right. And note that the user can decide to use a =
different separator and whether hierarchy is prefix or postfix in =
gnetlistrc, so it isn=92t as simple as looking for the last /.
>=20
>> 2. For genuinely hierarchical netlists, there's probably not a
>> single one-size-fits-all plug in solution. Not today.
>=20
> Sigh.
What do you expect? For Verilog, you can connect whole busses between =
levels, so you want that, but you may need to translate the bus syntax. =
For SPICE, you can=92t connect busses between levels, so you have to =
expand busses looking upward and downward. Upward is yet a different =
beast. At least SPICE isn=92t fussy about naming. Then there are several =
gnetlist back ends that are aware of hierarchy via the =
(gnetlist:get-renamed-nets) mechanism, but I don=92t understand how they =
use that information, so that=92s another case to consider.
>=20
>> 3. For pinseq-centered netlisting (SPICE), it needs to expand
>> pinseqs, too.
>=20
> My example expands two attributes; expanding three shouldn't be a
> problem.
Yep.
>=20
>> Another issue is that "-" seems a little strange as a range
>> token. ":" would match Verilog and some programming languages for
>> more user familiarity.
>=20
> I picked dash because common English uses it as a shortcut for "to",
> like "Copyright 1990-1995" or "meeting from 1-3pm". It made sense in
> a list context.
>=20
> Perl, C, and C++ use ".." (or "...") for ranges. It varies.
>=20
> Plus, consider that a layout "bus" connects to a list of usually
> non-sequential pin numbers. =46rom the pinnumber point of view, "A:B"
> syntax is less common than the "A,B,C" syntax.
Comma is fine, I think.
>=20
> OTOH the two syntaxes are orthogonal; one module could expand both -
> so you could say A[1:4] connects to pins "4-6,8".
>=20
> And I can see some folks getting confused about whether the :N means
> "to this number" or "for this many numbers". I.e. is A[4:2] A4,A3,A2
> or A4,A5 ? Unless you already know Verilog, it might be a stumbling
> point, esp if you've seen ":16" elsewhere to mean "a 16-bit bus".
>=20
> But in any case I'm not particularly tied to the syntax.
>=20
>> I suggest using Dirac-style angle brackets to designate a bus
>> definition, so a typical example might be "<nBL,A[8:2]>". While I
>> think a sufficiently aware gnetlist plugin could navigate this
>> without the extra tokens, we've historically exploited the
>> transparency of our formats to process schematics with other tools
>> as well. The extra tokens will help.
>=20
> I don't see how the extra syntax helps anything, as it would just add
> a "strip angle brackets around string" step. Busses would always only
> have <> around the whole string.
Not after hierarchical renaming. A plug-in could probe this with =
(gnetlist:get-renamed-nets), but I think it=92s more flexible and =
transparent to delimit the part of the name to be expanded. Of course, =
the reason I bring this up is that I=92m interested in other opinions.
>=20
> I.e. what's the difference in usability between these:
>=20
> <nBL,A[8:2]>
> nBL,A[8:2]
>=20
> I see no problem with just stripping out angle brackets, if that's
> what you mean.
>=20
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com
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