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Date:	Tue, 29 Dec 2015 15:16:23 -0500
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Subject:	Re: [geda-user] Project leadership (design error in the core of gschem)
From:	"Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To:	gEDA users mailing list <geda-user AT delorie DOT com>
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On Tue, Dec 29, 2015 at 3:05 PM, Svenn Are Bjerkem
(svenn DOT bjerkem AT googlemail DOT com) [via geda-user AT delorie DOT com]
<geda-user AT delorie DOT com> wrote:
> On 29 December 2015 at 20:35, John Doty <jpd AT noqsi DOT com> wrote:
>> I just do that with pins2gsch. Draw a small box for the FPGA, with a bus running to it. For my most recent project, the connections are extracted from the Vivado export, so when the FPGA designer scrambles pins on me, it automagically propagates to the netlist.
>
> Is that a graphical bus line, and is that bus actually connecting any
> pins with some kind of bus notation, or is it just cosmetic sugar?

Graphical buses as they are now are just cosmetic sugar. (good prose by the way)

I wanted to improve on this. There is stuff on the bugtracker.

> --
> Svenn
>



-- 
Home
http://evanfoss.googlepages.com/
Work
http://forge.abcd.harvard.edu/gf/project/epl_engineering/wiki/

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