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Mail Archives: geda-user/2015/12/28/18:10:47

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Subject: Re: [geda-user] Project leadership
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From: John Doty <jpd AT noqsi DOT com>
In-Reply-To: <CAGde_xPX8FB57SR-siOf5Udien1H04VVLd4fEFmJJDn30U4MvQ@mail.gmail.com>
Date: Mon, 28 Dec 2015 16:10:31 -0700
Message-Id: <60951D11-68FB-4184-910F-A201B7C2D079@noqsi.com>
References: <CAJXU7q_3XwthnN_8mp7B+-ShHeK+=7J=54ZavKBUG3S3bSKp2A AT mail DOT gmail DOT com> <CANEvwqiM7CKG+WpDRpG4L=HsmSEZ32=CBDyUhuk3ks-SNedL2Q AT mail DOT gmail DOT com> <43CC8F96-6452-40FA-9DFB-E0983721C19C AT noqsi DOT com> <CAGde_xPX8FB57SR-siOf5Udien1H04VVLd4fEFmJJDn30U4MvQ AT mail DOT gmail DOT com>
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On Dec 28, 2015, at 3:53 PM, Svenn Are Bjerkem =
(svenn DOT bjerkem AT googlemail DOT com) [via geda-user AT delorie DOT com] =
<geda-user AT delorie DOT com> wrote:

> On 28 December 2015 at 20:48, John Doty <jpd AT noqsi DOT com> wrote:
>> There are really two projects here: The original gEDA (now =
confusingly
>> called geda-gaf), and pcb. I think everyone agrees that pcb needs a =
lot of
>> work. On the other hand, geda-gaf is matiure, effective, and easy to =
extend
>> with scripting. Pcb development requires a great deal of =
collaboration.
>> Geda-gaf development mostly does not, as anybody can write and =
publish a
>> script.
>=20
> I would not call a generic schematic capture tool mature until it
> provides the designer use of buses and bus pins in his design without
> the need to actually name the nets to have connection.

I believe Paul Tan does this in his Verilog flow.

>=20
> --
> Svenn
>=20

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com



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