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Date:	Tue, 22 Dec 2015 17:05:01 -0900
Message-ID:	<CAC4O8c-oEf1n-EphBHqwARkEyLAeOF-3gYCrmQOXA55dMKh-TQ@mail.gmail.com>
Subject:	Re: [geda-user] Prop ... Structure? (Clearance calculation)
From:	"Britton Kerin (britton DOT kerin AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To:	geda-user AT delorie DOT com
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On Tue, Dec 22, 2015 at 1:02 PM, Peter Clifton (
petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com] <
geda-user AT delorie DOT com> wrote:

> > Then there is the problem is there is an unconnected object within
> distance but I guess it could worked around if not already done by at least
> temporary assign all objects to a net.
>
> I "think" this works ok, but I'm on a Win7 box with no PCB right now
> to check... OK, no wait - I did install PCB (remember it also ports to
> Win32 if you like masochism)...
>
>
> So - it "nearly" works.. two tracks violating DRC clearance, on a
> board with no netlist - no DRC results.
> Throw down a via, and touch it to one of those tracks - and we see 1x
> DRC violations - "Copper areas too close".
>
> Bug - one I'm sure could be fixed. We're probably just not iterating
> over all of the non "PV" type objects as potential DRC check
> start-points. (DRC draws a distinction between the in-layer objects
> like lines, arcs, polygons etc.. and the "PV" type objects (pin, via),
> which can traverse layers..
>

Yes this would be fairly straightforward to fix.  Variable clearance values
would be fairly easy to do as well, at least in an inefficient way:  find.c
uses a single global "bloat" value to check for connection changes at given
bloats (which can be negative).  To handle a board with variable clearance
requirements, you could just start with the lowest clearance and re-run the
entire board for each different clearance value.  If there weren't too
terribly many it wouldn't be too slow.  Traces with larger clearance
requirements probably also deserve larger overlap requirements, so you'd
probably actually need two additional passes for each "special" wire class.

Britton

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<div dir=3D"ltr"><br><div class=3D"gmail_extra"><br><div class=3D"gmail_quo=
te">On Tue, Dec 22, 2015 at 1:02 PM, Peter Clifton (<a href=3D"mailto:peter=
cjclifton AT googlemail DOT com">petercjclifton AT googlemail DOT com</a>) [via <a href=
=3D"mailto:geda-user AT delorie DOT com">geda-user AT delorie DOT com</a>] <span dir=3D"l=
tr">&lt;<a href=3D"mailto:geda-user AT delorie DOT com" target=3D"_blank">geda-use=
r AT delorie DOT com</a>&gt;</span> wrote:<br><blockquote class=3D"gmail_quote" st=
yle=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span=
 class=3D"">&gt; Then there is the problem is there is an unconnected objec=
t within distance but I guess it could worked around if not already done by=
 at least temporary assign all objects to a net.<br>
<br>
</span>I &quot;think&quot; this works ok, but I&#39;m on a Win7 box with no=
 PCB right now<br>
to check... OK, no wait - I did install PCB (remember it also ports to<br>
Win32 if you like masochism)...<br>
<br>
<br>
So - it &quot;nearly&quot; works.. two tracks violating DRC clearance, on a=
<br>
board with no netlist - no DRC results.<br>
Throw down a via, and touch it to one of those tracks - and we see 1x<br>
DRC violations - &quot;Copper areas too close&quot;.<br>
<br>
Bug - one I&#39;m sure could be fixed. We&#39;re probably just not iteratin=
g<br>
over all of the non &quot;PV&quot; type objects as potential DRC check<br>
start-points. (DRC draws a distinction between the in-layer objects<br>
like lines, arcs, polygons etc.. and the &quot;PV&quot; type objects (pin, =
via),<br>
which can traverse layers..<br></blockquote><div><br></div><div style=3D"">=
Yes this would be fairly straightforward to fix.=C2=A0 Variable clearance v=
alues would be fairly easy to do as well, at least in an inefficient way: =
=C2=A0find.c uses a single global &quot;bloat&quot; value to check for conn=
ection changes at given bloats (which can be negative).=C2=A0 To handle a b=
oard with variable clearance requirements, you could just start with the lo=
west clearance and re-run the entire board for each different clearance val=
ue.=C2=A0 If there weren&#39;t too terribly many it wouldn&#39;t be too slo=
w.=C2=A0 Traces with larger clearance requirements probably also deserve la=
rger overlap requirements, so you&#39;d probably actually need two addition=
al passes for each &quot;special&quot; wire class.</div><div style=3D""><br=
></div><div style=3D"">Britton</div><div>=C2=A0</div></div><br></div></div>

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