Mail Archives: geda-user/2015/12/22/18:02:19
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On Dec 22, 2015, at 2:43 PM, Peter Clifton =
(petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com] =
<geda-user AT delorie DOT com> wrote:
> I think your suggested flow captures it...
>=20
> I'm presuming ueda has an element which can parse the verilog into a
> PCB netlist.
>=20
>=20
> Longer term, I'd love to see the "core" ("EdaCore" or "openEDA" -
> whatever) library support the primitive concept of netlists, and we
> could just teach _that_ to read verilog, as well as the gschem stuff
> (then merge from multiple sources into one netlist - and spit out via
> whatever backend / plugin suits your target environment).
I=92ve been doing that merge for years. There may be a more elegant way, =
but my way works without any difficulty.
http://www.gedasymbols.org/user/john_doty/tools/pins2gsch.html
Also, I put the data into my LaTeX docs as tables alongside the =
schematics. Very handy when you=92re probing a connector in test.
http://www.gedasymbols.org/user/john_doty/tools/pins2tex.html
Three column TSV representation makes netlist fragments easy to process. =
Here=92s a script that joins a pin map from Vivado to a pin name to net =
name map and generates suitable input for pins2gsch:
=
https://github.com/TESScience/FPE/blob/master/FPE/Schematic/makeFPGApinmap=
.awk
>=20
> Bonus points for PCB using the core-library too, so it can "give up"
> its one preferred on-disk netlist format, and read any useful ones we
> care to implement a reader for in the core EDA library.
I=92m quite skeptical of a core library. An agreed-upon external data =
representation is handy, but tool writers will want their own internal =
representations in their own languages for their own problems.
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com
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