X-Authentication-Warning:	delorie.com: mail set sender to geda-user-bounces using -f
X-Recipient:	geda-user AT delorie DOT com
X-Original-DKIM-Signature:	v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=googlemail.com; s=20120113;
	h=mime-version:in-reply-to:references:date:message-id:subject:from:to
	:content-type:content-transfer-encoding;
	bh=8QS1WTmNSyhX/6R4JPvZzD7OlUbStZcBvtuITLQGpro=;
	b=NtI117I0eGkgSD17L+DayyPzSjgB9OWD8qdvLydgppKYhb1RILgnXi3QPuqurGYCwp
	rWrzIztXeL62scxqEjcLPMd7YSfntl9Pa/dHiN1oIKQ68+AicTgnYG2jgCofDo328MhS
	K3eZHjkLTSiNi3f8fuBZm0fbqarlNHq0qysaQi3ASWK8RHGpHFjaTJRUCROWc8yi9V/d
	ZhJ1moRo5sPUovB+/StxsqkhS3m6xY+sxULyhv5VcOYDTE52K1WAztw4VrCq9Ld17QwH
	809Dd309/7/tWGW3/4KIIyikJDw2607pxXC9mNxAsjKnYN5Whv7JIafx/liF0rrSakAX
	EkrQ==
MIME-Version:	1.0
X-Received:	by 10.202.201.77 with SMTP id z74mr11936539oif.24.1450820608134;
	Tue, 22 Dec 2015 13:43:28 -0800 (PST)
In-Reply-To:	<s6n37uumanm.fsf@blaulicht.dmz.brux>
References:	<1512221837 DOT AA25291 AT ivan DOT Harhan DOT ORG>
	<CAJXU7q_mXmipJ1fLvLpuLvnYjktV2SHoA+bG=L5+E-EfdygeOA AT mail DOT gmail DOT com>
	<s6n37uumanm DOT fsf AT blaulicht DOT dmz DOT brux>
Date:	Tue, 22 Dec 2015 21:43:28 +0000
Message-ID:	<CAJXU7q_qxdvJaejF-VcY=u7VHZ-zrfrc+Z7-qSwfFyPdy-umxw@mail.gmail.com>
Subject:	Re: [geda-user] Project leadership
From:	"Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To:	gEDA User Mailing List <geda-user AT delorie DOT com>
X-MIME-Autoconverted:	from quoted-printable to 8bit by delorie.com id tBMLhVP1015444
Reply-To:	geda-user AT delorie DOT com
Errors-To:	nobody AT delorie DOT com
X-Mailing-List:	geda-user AT delorie DOT com
X-Unsubscribes-To:	listserv AT delorie DOT com

I think your suggested flow captures it...

I'm presuming ueda has an element which can parse the verilog into a
PCB netlist.


Longer term, I'd love to see the "core" ("EdaCore" or "openEDA" -
whatever) library support the primitive concept of netlists, and we
could just teach _that_ to read verilog, as well as the gschem stuff
(then merge from multiple sources into one netlist - and spit out via
whatever backend / plugin suits your target environment).

Bonus points for PCB using the core-library too, so it can "give up"
its one preferred on-disk netlist format, and read any useful ones we
care to implement a reader for in the core EDA library.

Peter

On 22 December 2015 at 21:33, Stephan Böttcher <geda AT psjt DOT org> wrote:
>
> "Peter Clifton (petercjclifton AT googlemail DOT com) [via
> geda-user AT delorie DOT com]" <geda-user AT delorie DOT com> writes:
>
>> I really believe you are on to a very strong concept here...
>> schematics have their place IMO, but look at many modern designs
>> (laptop etc., say?) and see how that graphical the format of
>> schematics is really being pushed beyond its most effective.
>
> People tell me that a schematic drawing should illustrate the function
> of a circuit.  But most of that function is hidden inside the µC and
> FPGA.  So, my symbols and schematics are more a preview of the layout,
> to get a good first shot at (functionally arbitrary) pin assignements.
>
> Like this one:  http://www.ieap.uni-kiel.de/et/people/stephan/rpirena/
>
> I thought about using Verilog as netlist format for PCBs.  How would I
> convert those to pcb netlists, with some graphical drawings added in the
> mix?
>
>  gschem, gnetlist --> Verilog
>  Verilog --> ueda --> PCB netlist
>
> ?
>
> --
> Stephan
>

- Raw text -