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Date:	Tue, 22 Dec 2015 20:27:49 +0000
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Subject:	Re: [geda-user] Proposing a New Hierarchical Data Structure?
From:	"Peter Clifton (petercjclifton AT googlemail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On 22 December 2015 at 19:42, Nicklas Karlsson
(nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com]
<geda-user AT delorie DOT com> wrote:

> What we arguing about is usually not real problems or any problems at all, usually it is the best method to implement something
...

> Only real problems I could find is copper overlap and clearance. What pcb really lack is different clearance between different nets. Implementing stuff like selection of clearance and trace width from net attributes or similar should be straight forward although their may be a lot of arguing about best method to implement.

How PCB works this out, is by bloating individual net elements, and
checking to see if by enlarging the track by the minimum DRC
clearance, whether or not it changes the netlist connectivity. (E.g.
if this track were fatter by 0.5mm, would it change the netlist ->
clearance must be <0.5mm).

Actually working out the minimum distance would take some more
creative algorithms I think - although should not be overwhelmingly
different.


Regarding net-classes and clearances... this has LONG been on my
wishlist... I would love if you wanted to implement it.

The case I'd have was PSUs, where you might have line-side connected
nets, and secondary-side connected nets. You would then specify a
clearance between the groups (derived from the regulatory rules).

Alternative use-cases, HV multipliers - nets tagged with nominal
voltages, or pair-wise net data on differential voltages. (And a rule
to translate maximum voltages into a minimum clearance).

Noisy / clean signals might also be interesting to track.


For me:
Step 1 is figure out how to specify the driving data.
Step 2 is add this to the internal data model
Step 3 is provide ways to load (and possibly save) the data
Step 4 is provide a DRC check to test against the data
Step 5 is update / tweak online DRC checks to show / enforce clearance
requirements during actual tracking


Let me know if I can be of any help if you decide to proceed. Its been
a while since I braved PCB's DRC code, but I was at one point familiar
with it.

Peter

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