Mail Archives: geda-user/2015/12/22/15:09:15
Hi Mychaela,
Sorry if I was poking fun earlier in my email - it was meant in good humor.
I really believe you are on to a very strong concept here...
schematics have their place IMO, but look at many modern designs
(laptop etc., say?) and see how that graphical the format of
schematics is really being pushed beyond its most effective.
A structural verilog subset seems to be the favorite (I'm biased as I
like the idea) way to do text based circuit entry, and should
hopefully scale well to modular designs.
gnucap (if you're familiar with that), uses a structural verilog
format as its native netlist input.
Best wishes,
Peter
On 22 December 2015 at 18:37, Mychaela Falconia <falcon AT ivan DOT harhan DOT org> wrote:
> Peter Clifton (petercjclifton AT googlemail DOT com) wrote:
>
>> I didn't want to call anyone out by name,
>
> I'm glad you didn't, as the name by which you probably know me - the
> name by which I went all those years ago - is not my current name any
> more.
>
> I am still around, but I have changed my sex, and got a new name to go
> with it. :-)
>
>> but if you recall - there
>> was an individual who forked gEDA,
>
> I am not sure if "forked" is the proper term to use here, as I did not
> take any code whatsoever from gEDA, only some concepts.
>
>> and ported to a text-mode schematic
>> entry system... (no problem with that - especially given it worked for
>> him).
>
> It worked very well, and still does work, although I am no longer a
> "he". :)
>
>> I can't recall whether it was genuinely a PDP-10 he was running,
>> but I do recall being impressed by the level of retro-computing at the
>> time.
>
> VAX, not PDP-10, running 4.3BSD UNIX.
>
>> I think he called the fork uEDA?
>
> The current incarnation lives here:
>
> https://bitbucket.org/falconian/ueda-linux
>
>> I regret not having tried it, as the
>> concept actually had a lot of charm for certain types of circuit
>> (ironically - probably more so with more modern designs that have more
>> plumbing, and less analogue electronics!).
>
> When I had to revisit my tools earlier in 2015 in conjunction with
> starting a new board design project (I am mostly a software girl, and
> only get to do hw design on the order of one major PCB project per
> decade), I realized that my earlier uschem approach (having
> non-graphical "schematic sheets" with connections by name in a totally
> flat netname space) was a dead end, so I retired that code and wrote
> an entirely new system which you can find in the source repository
> linked above.
>
> My new non-graphical, text-based "schematic" design entry language is
> the structural subset of Verilog (wires, ports and instantiations),
> and I make very heavy use of hierarchy to make readable designs that
> can be evaluated for correctness. Here is my current project done
> with these tools:
>
> https://bitbucket.org/falconian/freecalypso-schem
>
> M~
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