Mail Archives: geda-user/2015/09/13/18:09:17
> > Aside from assigning GUIDs to each symbol as they're instantiated, I
> > don't have a good solution to this.
>
> The refdes assigned in the schematic is the GUID, just as
> always. Similarly, the pin number assigned in the symbol, after
> translation via the slot number assigned in the schematic, is the
> pin's GUID. Those don't change, but what the user sees in the
> graphics might.
If you have a 7400, you already have four gates (and thus four
symbols) with the same refdes. It's already not a GUID (globally
unique identifer) because it's not even unique within the page,
because saying "U4" doesn't tell you which of those four symbols
you're referring to. Saying "the U4 that had pin 2" might work,
unless we do away with numberic pins in favor of symbolic ones, then
all four gates have pins A,B,Y - not unique either. With a symbolic
light symbol like that, pin and gate assignment might happen much
later, so device "U4" on the layout might include gates from U3, U7,
U5, and U14. If you want to do an as-built of that, you need to know
*which* U3 symbol, *which* U7 symbol, etc.
The only way to let the refdes be a UID (much less a GUID) is to
enforce it in gschem and gnetlist - a hard error if you reuse one -
and assume that slotting is going to make a new, probably messy,
refdes in the layout. And that just makes the power pin problem
worse, plus stops people from splitting a large chip into mutltiple
symbols.
In my sch2csv script, I use the X,Y coordinate of the symbol on the
page and the file it came from as it's GUID, assuming that two symbols
won't be in the same place on the same page, but even that's not
guaranteed to be unique. But at least "the U4 that's at 325,400" has
a better chance of picking exactly one symbol :-)
> Good point. I think the solution is to allow the refdes to be a
> pathname. This already works downward, but,
Yea, I figured no matter how messy identifiers turned out, identifiers
in a flattened heirarchy were going to be messier. You end up with at
best a refdes like CP7.A4.U3 for gate U3 in amplifier instance 4 of
control processor instance 7.
The messiness could be partly controlled if the layout could designate
a region of the board as being a location in the heirarchy, so
shortcut refdes's could be used on the silkscreen. I.e. a region
would be outlined and the outline named "CP7.A4" and within that
outline, the text ".U4" would imply "CP7.A4.U4".
However, I'm guessing heirarchical layout could be arbitrarily complex
in itself. It would be nice to only have to layout each subsection
once and have that repeat, but that assumes each section can be laid
out exactly the same. The ASIC folks seem to have this down pat but
their tools are already more complex than ours.
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