Mail Archives: geda-user/2015/09/11/06:41:13
I don't think you are going to have any problems. I've worked with
layout guys who routinely have 0 clearance on the soldermask. The board
fab houses will adjust their process, sometimes without telling you. At
work, we use a pretty good place, and they will adjust the clearance up
or down as needed. I think the fab houses have to make adjustments to
your design in order to work with the tolerances of their own processes.
Anyway, you can ask the fab house if they fix that sort of stuff up or
not.
good luck
gene
On Thu, Sep 10, 2015 at 07:05 AM, Matt Rhys-Roberts
(matt DOT rhys-roberts AT envinsci DOT co DOT uk) [via geda-user AT delorie DOT com] wrote:
> (pcb ver. 20110918, Ubuntu 14.04 LTS)
>
> I've just submitted final Gerber files for the production of a small
> run of prototype 2-sided boards, and all went well... except where I'd
> created a footprint that had zero "soldermask-to-copper-edge"
> clearance, which was my fault due to my inexperience in creating SMT
> footprints :) . As there was no time to correct and re-send the files,
> I'll just physically carve the 20 affected pads away from the ground
> plane that's enveloped them, on each board.
>
> I spent considerable time refreshing the DRC window, as I completed
> both ground planes and ground vias to the board. I used thermal
> patterns to connect un-netted vias to top and bottom ground planes,
> which caused many warnings about traces being too thin, so I kept
> trying different things until the DRC list cleared.
>
> Anyway, at no time did it detect that the ground plane had shorted
> with nets that it should not have, caused my faulty footprint design.
>
> So, I wonder if there's any method of catching this if it happens next
> time? Should I have had DRC options set differently? Is this detected
> in later versions? Are shorted nets detectable by some other means?
>
> Many thanks,
>
> Matt.
>
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