Mail Archives: geda-user/2015/09/09/14:06:38
On Sep 9, 2015, at 11:37 AM, DJ Delorie <dj AT delorie DOT com> wrote:
>
>> In my implementation, busses are exactly that: net-like objects with more
>> than one signal. "netname=D[0..15]" is a valid attribute for a bus and is
>> equivalent to setting "netname=D0" to "netname=D15" on the individual
>> nets.
>
> If we allow a net to be more than one signal (which verilog allows, so
> precedent ;) then buses *are* nets, and we don't need anything new,
> other than to teach the netlisters how to deal with a non-singular
> net connecting to a non-singular pin.
Except that unlike nets, buses can be composed and sliced. For example, a processor bus may connect directly to a backplane bus, but they aren’t the same.
>
>> This is still how nets are connected to busses (remember, I didn't change
>> the way bus rippers work). For example, in the subsheet "resistors.sch"
>> of my example schematic, I assigned the netname "left[7..0]" to a bus and
>> then assigned the netnames "left7" to "left0" to a bunch of nets. For
>> clarity, I didn't use bus rippers, but I obviously could have done.
>
> In this example, with current software, there's no need to assign
> names to bus symbols - the fact that the nets are named is sufficient
> to cause connectivity. What benefit, then, of naming the bus symbols?
To distinguish the bus from its constituent busses and nets.
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com
- Raw text -