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Date:	Mon, 13 Jul 2015 18:45:29 -0700
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Subject:	Re: [geda-user] PCB interface (ECAD vs. MCAD)
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On Mon, Jul 13, 2015 at 6:01 PM, Kai-Martin Knaak <kmk AT familieknaak DOT de>
wrote:

> Ouabache Designworks (z3qmtr45-
> Re5JQEeQqe8AvxtiuMwx3w AT public DOT gmane DOT org) [via geda-user-
> Ht4Cp5ncgjRBDgjK7y7TUQ AT public DOT gmane DOT org] wrote:
>
> > I'm
> > surprised that no one has applied autorouting to schematic capture,
> > That would really be usefull.
>
> Schematic capture serves two purposes. It is the way the electronics
> designer tells the computer about the connections he needs in the
> netlist. And it also is meant to present the topology of the circuit
> to the human eye as comprehensibly as possible. A readable schematic
> asks for much more than "connect all these pins with lines".
>
> An auto router needs to be told which pins to connect. In other words,
> it needs a netlist. But it is the main purpose of schematic capture to
> create a netlist in the first place.
>
> ---<)kaimartin(>---
>

Nothing is worse than a completely machine generated schematic. It's
nothing more than a graphical netlist. But you could start by reading in a
netlist to get all the components and connections and then use a ratsnest
to figure out the best component placements while still maintaining all the
connections. Once you have a placement that minimizes net lengths and
represents major signal flow you can use the autorouter to make all the
nets nicely spaced and orthonginal. If not perfect then hand tweek from
there.

You do need a graphics engine that gives you a choice of quality
fonts,sizes and spacing for publication.

This is where the IC world screwed up. 20 Years ago we designed IC's using
schematic capture but our chips were growing so fast that you couldn't lay
down gates fast enough to meet schedule. This led to the shift from
Schematics to HDLs. The problem was that only the leaf level component
designers were having a problem. The architects were fine because they were
doing the top levels that interconnected the leaf levels and were happy
with schematics. They liked to design with block diagrams and used
schematics for that purpose. When they had to switch over to hdls they
started using tools like visio for their diagrams and these were not linked
to the actual connectivity.

We need to create a schematic capture tool that can read/write netlists.
This could spur a return of ic architects using our tool for block diagrams.

John Eaton

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Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr"><br><div class=3D"gmail_extra"><br><div class=3D"gmail_quo=
te">On Mon, Jul 13, 2015 at 6:01 PM, Kai-Martin Knaak <span dir=3D"ltr">&lt=
;<a href=3D"mailto:kmk AT familieknaak DOT de" target=3D"_blank">kmk AT familieknaak.=
de</a>&gt;</span> wrote:<br><blockquote class=3D"gmail_quote" style=3D"marg=
in:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Ouabache Designw=
orks (z3qmtr45-<br>
<a href=3D"mailto:Re5JQEeQqe8AvxtiuMwx3w AT public DOT gmane DOT org">Re5JQEeQqe8Avxti=
uMwx3w AT public DOT gmane DOT org</a>) [via geda-user-<br>
<span class=3D""><a href=3D"mailto:Ht4Cp5ncgjRBDgjK7y7TUQ AT public DOT gmane DOT org"=
>Ht4Cp5ncgjRBDgjK7y7TUQ AT public DOT gmane DOT org</a>] wrote:<br>
<br>
&gt; I&#39;m<br>
&gt; surprised that no one has applied autorouting to schematic capture,<br=
>
&gt; That would really be usefull.<br>
<br>
</span>Schematic capture serves two purposes. It is the way the electronics=
<br>
designer tells the computer about the connections he needs in the<br>
netlist. And it also is meant to present the topology of the circuit<br>
to the human eye as comprehensibly as possible. A readable schematic<br>
asks for much more than &quot;connect all these pins with lines&quot;.<br>
<br>
An auto router needs to be told which pins to connect. In other words,<br>
it needs a netlist. But it is the main purpose of schematic capture to<br>
create a netlist in the first place.<br>
<br>
---&lt;)kaimartin(&gt;---<br></blockquote><div><br></div><div>Nothing is wo=
rse than a completely machine generated schematic. It&#39;s nothing more th=
an a graphical netlist. But you could start by reading in a netlist to get =
all the components and connections and then use a ratsnest to figure out th=
e best component placements while still maintaining all the connections. On=
ce you have a placement that minimizes net lengths and represents major sig=
nal flow you can use the autorouter to make all the nets nicely spaced and =
orthonginal. If not perfect then hand tweek from there.<br><br></div><div>Y=
ou do need a graphics engine that gives you a choice of quality fonts,sizes=
 and spacing for publication.<br><br></div><div>This is where the IC world =
screwed up. 20 Years ago we designed IC&#39;s using schematic capture but o=
ur chips were growing so fast that you couldn&#39;t lay down gates fast eno=
ugh to meet schedule. This led to the shift from Schematics to HDLs. The pr=
oblem was that only the leaf level component designers were having a proble=
m. The architects were fine because they were doing the top levels that int=
erconnected the leaf levels and were happy with schematics. They liked to d=
esign with block diagrams and used schematics for that purpose. When they h=
ad to switch over to hdls they started using tools like visio for their dia=
grams and these were not linked to the actual connectivity.<br><br></div><d=
iv>We need to create a schematic capture tool that can read/write netlists.=
 This could spur a return of ic architects using our tool for block diagram=
s.<br><br></div><div>John Eaton<br><br><br></div><div><br></div><div>=C2=A0=
<br></div></div><br></div></div>

--001a113f648e407cf3051acbfef7--

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