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Date:	Thu, 9 Jul 2015 23:38:57 +0000
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Subject:	Re: [geda-user] What is the hardest part in a PCB layout program?
From:	"Evan Foss (evanfoss AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
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On 7/9/15, DJ Delorie <dj AT delorie DOT com> wrote:

snip

>
>> OT: Is DRC checking done via the rendering engine or is there a
>> separate geometry engine that does this and verifies when traces and
>> etc are connected?
>
> There's a geometry engine in DRC although how it works is totally
> counter-intuitive:
>
> * Generate a netlist based on connectivity. (also used by the rats
>   list stuff, find, select-nets, etc)
>
> * Now, increase the size of everything by N and generate a new netlist.
>
> * Are the netlists different?  Bug!

I don't find that counter intuitive. It was just finding the geometry
engine in the other source was not obvious. (I might, probably did,
give up too quickly)

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