Mail Archives: geda-user/2014/08/04/08:37:13
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On Aug 4, 2014, at 7:48 AM, Stuart Brorson <sdb AT cloud9 DOT net> wrote:
> Hi --
>=20
>>> Many symbol creators don?t seem to
>>> understand pinseq.
>>=20
>> For SPICE, I'm thinking of using a unique attribute, say "pinnode". =
So we
>> could part the two workflows - simulation in SPICE and making pcb's.
>> I believe that in general every particular workflow should lean on =
its
>> own attributes in gEDA/gaf.
>=20
> Overloading pinseq for use with spice-sdb seems to have caused a lot
> more grief than I could have imagined at the time. I think the idea
> of separating the workflows makes sense. Moreover, eliminating the
> overload would be a good thing. I would do it be modifying spice-sdb
> to use a different atribute, for example pinnode, as you say. Or
> spicepin, or something like that.
See https://github.com/noqsi/gnet-spice-noqsi. Its spice-prototype =
attribute is very flexible. It controls refdes munging, connections, =
parameters, etc. Connections can be ordered by pinseq or in arbitrary =
order by pinnumber (much handier for slotted components). If you turn =
off gnetlist=92s hierarchy expansion, spice-noqsi can turn hierarchical =
blocks developed for layout into SPICE subcircuits, and interpret the =
corresponding symbols correctly. Here=92s an example of a =93test =
fixture=94 for a subcircuit. The symbol and the underlying source =
schematic (which, unfortunately, I cannot publish) don=92t change *at =
all* when I use them in a printed circuit netlist flow.
--Apple-Mail=_80E14F06-B5FE-4BE5-8B9C-0DA7A4B27CEC
Content-Disposition: attachment;
filename=HV_reg_test.sch
Content-Type: application/octet-stream;
name="HV_reg_test.sch"
Content-Transfer-Encoding: 7bit
v 20130925 2
C 40000 40000 0 0 0 EMBEDDEDNoqsi-title-B.sym
[
B 40000 40000 17000 11000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 54400 41500 5 10 0 0 0 0 1
graphical=1
L 52900 40600 52900 40000 15 0 0 0 -1 -1
B 49400 40000 7600 1400 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 49400 40700 57000 40700 15 0 0 0 -1 -1
T 50000 40500 9 10 0 1 0 0 1
date=$Date: 2010-02-10 22:01:20 $
T 53900 40500 9 10 0 1 0 0 1
rev=$Revision: 1.2 $
T 55400 40200 9 10 0 1 0 0 1
auth=$Author: jpd $
T 50200 40800 9 8 0 1 0 0 1
fname=$Source: /cvs/Osaka/SXI/Components/Symbols/Noqsi-title-B.sym,v $
T 53200 41200 9 14 0 1 0 4 1
title=TITLE
T 49500 40800 15 8 1 0 0 0 1
FILE:
T 53000 40500 15 8 1 0 0 0 1
REVISION:
T 53000 40200 15 8 1 0 0 0 1
DRAWN BY:
T 49500 40200 15 8 1 0 0 0 1
PAGE
T 51200 40200 15 8 1 0 0 0 1
OF
T 49500 41200 15 8 1 0 0 0 1
TITLE
T 49500 40500 15 8 1 0 0 0 1
DATE
B 49400 49600 7600 1400 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 50200 50400 9 30 1 0 0 0 1
Noqsi Aerospace, Ltd.
T 50600 50100 9 10 1 0 0 0 1
2822 South Nova Road, Pine, Colorado, USA 80470
T 51300 49800 9 10 1 0 0 0 1
+1-303-816-2756 jpd AT noqsi DOT com
]
{
T 50000 40500 5 10 1 1 0 0 1
date=$Date: 2010-02-10 22:01:20 $
T 53900 40500 5 10 1 1 0 0 1
rev=$Revision: 1.2 $
T 55400 40200 5 10 1 1 0 0 1
auth=$Author: jpd $
T 50200 40800 5 8 1 1 0 0 1
fname=$Source: /cvs/Osaka/SXI/Components/Symbols/Noqsi-title-B.sym,v $
T 53200 41200 5 14 1 1 0 4 1
title=TITLE
}
C 46900 45100 1 0 0 EMBEDDEDgnd-1.sym
[
P 47000 45200 47000 45400 1 0 1
{
T 47058 45261 5 4 0 1 0 0 1
pinnumber=1
T 47058 45261 5 4 0 0 0 0 1
pinseq=1
T 47058 45261 5 4 0 1 0 0 1
pinlabel=1
T 47058 45261 5 4 0 1 0 0 1
pintype=pwr
}
L 46900 45200 47100 45200 3 0 0 0 -1 -1
L 46955 45150 47045 45150 3 0 0 0 -1 -1
L 46980 45110 47020 45110 3 0 0 0 -1 -1
T 47200 45150 8 10 0 0 0 0 1
net=GND:1
]
C 41500 45000 1 0 0 EMBEDDEDgnd-1.sym
[
P 41600 45100 41600 45300 1 0 1
{
T 41658 45161 5 4 0 1 0 0 1
pinnumber=1
T 41658 45161 5 4 0 0 0 0 1
pinseq=1
T 41658 45161 5 4 0 1 0 0 1
pinlabel=1
T 41658 45161 5 4 0 1 0 0 1
pintype=pwr
}
L 41500 45100 41700 45100 3 0 0 0 -1 -1
L 41555 45050 41645 45050 3 0 0 0 -1 -1
L 41580 45010 41620 45010 3 0 0 0 -1 -1
T 41800 45050 8 10 0 0 0 0 1
net=GND:1
]
N 45800 46500 41600 46500 4
{
T 43700 46600 5 10 1 1 0 0 1
netname=in
}
C 45000 47200 1 0 0 EMBEDDEDvdc-1.sym
[
T 45700 47850 8 10 0 1 0 0 1
refdes=V?
T 45700 48050 5 10 0 0 0 0 1
device=VOLTAGE_SOURCE
T 45700 48250 5 10 0 0 0 0 1
footprint=none
T 45700 48450 5 10 0 0 0 0 1
numslots=0
T 45700 48650 5 10 0 0 0 0 1
description=dc power source
P 45300 48400 45300 48100 1 0 0
{
T 45350 48200 5 8 1 1 0 0 1
pinnumber=1
T 45350 48200 5 8 0 1 0 2 1
pinseq=1
T 45300 48050 9 8 1 1 0 5 1
pinlabel=+
T 45300 47900 5 8 0 1 0 5 1
pintype=pwr
}
P 45300 47200 45300 47500 1 0 0
{
T 45350 47300 5 8 1 1 0 0 1
pinnumber=2
T 45350 47300 5 8 0 1 0 2 1
pinseq=2
T 45300 47550 9 8 1 1 0 3 1
pinlabel=-
T 45300 47700 5 8 0 1 0 3 1
pintype=pwr
}
V 45300 47800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 45175 47825 45425 47825 3 0 0 0 -1 -1
L 45175 47775 45425 47775 3 0 0 0 -1 -1
T 45700 47650 5 10 0 1 0 0 1
value=DC 1V
]
{
T 45700 47850 5 10 1 1 0 0 1
refdes=Vp
T 45700 47650 5 10 1 1 0 0 1
value=DC 5V
}
C 45200 46900 1 0 0 EMBEDDEDgnd-1.sym
[
P 45300 47000 45300 47200 1 0 1
{
T 45358 47061 5 4 0 1 0 0 1
pinnumber=1
T 45358 47061 5 4 0 0 0 0 1
pinseq=1
T 45358 47061 5 4 0 1 0 0 1
pinlabel=1
T 45358 47061 5 4 0 1 0 0 1
pintype=pwr
}
L 45200 47000 45400 47000 3 0 0 0 -1 -1
L 45255 46950 45345 46950 3 0 0 0 -1 -1
L 45280 46910 45320 46910 3 0 0 0 -1 -1
T 45500 46950 8 10 0 0 0 0 1
net=GND:1
]
N 45300 48400 47000 48400 4
N 47000 48400 47000 47200 4
N 48700 46500 48200 46500 4
{
T 48400 46600 5 10 1 1 0 0 1
netname=out
}
C 45800 45400 1 0 0 EMBEDDEDHVregulator.sym
[
B 46100 45700 1800 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 48300 48200 9 10 0 0 0 0 1
source=HVregulator.sch
T 48300 48400 9 10 0 0 0 0 1
description=HV Regulator
T 48300 48600 9 10 0 0 0 0 1
device=HVregulator
T 48300 48800 9 10 0 0 0 0 1
distlicense=GPL
T 48300 49000 9 10 0 0 0 0 1
uselicense=unlimited
T 48300 49200 9 10 0 0 0 0 1
author=jpd AT noqsi DOT com
T 48300 49400 9 10 0 0 0 0 1
copyright=2014 John P. Doty
T 47600 47000 9 10 0 1 0 3 1
refdes=HV?
T 47000 46200 9 10 1 1 0 3 1
HV Regulator
P 45800 46500 46100 46500 1 0 0
{
T 46150 46500 9 10 1 1 0 1 1
pinlabel=HVin
T 46000 46550 5 8 0 1 0 6 1
pinnumber=1
T 46000 46550 5 8 0 1 0 6 1
pinseq=1
T 46000 46550 9 10 0 1 0 6 1
pintype=pas
}
P 47000 47200 47000 46900 1 0 0
{
T 47000 46850 9 10 1 1 0 5 1
pinlabel=+5V
T 47050 46950 5 8 0 1 0 0 1
pinnumber=6
T 47050 46950 5 8 0 1 0 0 1
pinseq=6
T 46900 44650 9 10 0 1 0 6 1
pintype=pas
}
P 47000 45400 47000 45700 1 0 0
{
T 47000 45750 9 10 1 1 0 3 1
pinlabel=GND
T 47050 45650 5 8 0 1 0 2 1
pinnumber=8
T 47050 45650 5 8 0 1 0 2 1
pinseq=8
T 46900 45450 9 10 0 1 0 6 1
pintype=pas
}
P 48200 46500 47900 46500 1 0 0
{
T 47850 46500 9 10 1 1 0 7 1
pinlabel=HVout
T 48000 46550 5 8 0 1 0 0 1
pinnumber=9
T 48000 46550 5 8 0 1 0 0 1
pinseq=9
T 47800 46550 9 10 0 1 0 6 1
pintype=pas
}
T 48300 48000 8 10 0 0 0 0 1
spice-prototype=X? %down HVregulator
P 45800 46000 46100 46000 1 0 0
{
T 46150 46000 9 10 1 1 0 1 1
pinlabel=DAC
T 46000 46050 5 8 0 1 0 6 1
pinnumber=2
T 46000 46050 5 8 0 1 0 6 1
pinseq=2
T 46000 46050 9 10 0 1 0 6 1
pintype=pas
}
P 48200 46000 47900 46000 1 0 0
{
T 47850 46000 9 10 1 1 0 7 1
pinlabel=HK
T 48000 46050 5 8 0 1 0 0 1
pinnumber=3
T 48000 46050 5 8 0 1 0 0 1
pinseq=3
T 47800 46050 9 10 0 1 0 6 1
pintype=pas
}
]
{
T 47600 47000 5 10 1 1 0 3 1
refdes=HV1
}
C 41300 45300 1 0 0 EMBEDDEDvdc-1.sym
[
T 42000 45950 8 10 0 1 0 0 1
refdes=V?
T 42000 46150 5 10 0 0 0 0 1
device=VOLTAGE_SOURCE
T 42000 46350 5 10 0 0 0 0 1
footprint=none
T 42000 46550 5 10 0 0 0 0 1
numslots=0
T 42000 46750 5 10 0 0 0 0 1
description=dc power source
P 41600 46500 41600 46200 1 0 0
{
T 41650 46300 5 8 1 1 0 0 1
pinnumber=1
T 41650 46300 5 8 0 1 0 2 1
pinseq=1
T 41600 46150 9 8 1 1 0 5 1
pinlabel=+
T 41600 46000 5 8 0 1 0 5 1
pintype=pwr
}
P 41600 45300 41600 45600 1 0 0
{
T 41650 45400 5 8 1 1 0 0 1
pinnumber=2
T 41650 45400 5 8 0 1 0 2 1
pinseq=2
T 41600 45650 9 8 1 1 0 3 1
pinlabel=-
T 41600 45800 5 8 0 1 0 3 1
pintype=pwr
}
V 41600 45900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 41475 45925 41725 45925 3 0 0 0 -1 -1
L 41475 45875 41725 45875 3 0 0 0 -1 -1
T 42000 45750 5 10 0 1 0 0 1
value=DC 1V
]
{
T 42000 45950 5 10 1 1 0 0 1
refdes=Vhv
T 42000 45750 5 10 1 1 0 0 1
value=DC -180V
}
C 45700 43800 1 0 0 EMBEDDEDgnd-1.sym
[
P 45800 43900 45800 44100 1 0 1
{
T 45858 43961 5 4 0 1 0 0 1
pinnumber=1
T 45858 43961 5 4 0 0 0 0 1
pinseq=1
T 45858 43961 5 4 0 1 0 0 1
pinlabel=1
T 45858 43961 5 4 0 1 0 0 1
pintype=pwr
}
L 45700 43900 45900 43900 3 0 0 0 -1 -1
L 45755 43850 45845 43850 3 0 0 0 -1 -1
L 45780 43810 45820 43810 3 0 0 0 -1 -1
T 46000 43850 8 10 0 0 0 0 1
net=GND:1
]
C 45500 44100 1 0 0 EMBEDDEDvdc-1.sym
[
T 46200 44750 8 10 0 1 0 0 1
refdes=V?
T 46200 44950 5 10 0 0 0 0 1
device=VOLTAGE_SOURCE
T 46200 45150 5 10 0 0 0 0 1
footprint=none
T 46200 45350 5 10 0 0 0 0 1
numslots=0
T 46200 45550 5 10 0 0 0 0 1
description=dc power source
P 45800 45300 45800 45000 1 0 0
{
T 45850 45100 5 8 1 1 0 0 1
pinnumber=1
T 45850 45100 5 8 0 1 0 2 1
pinseq=1
T 45800 44950 9 8 1 1 0 5 1
pinlabel=+
T 45800 44800 5 8 0 1 0 5 1
pintype=pwr
}
P 45800 44100 45800 44400 1 0 0
{
T 45850 44200 5 8 1 1 0 0 1
pinnumber=2
T 45850 44200 5 8 0 1 0 2 1
pinseq=2
T 45800 44450 9 8 1 1 0 3 1
pinlabel=-
T 45800 44600 5 8 0 1 0 3 1
pintype=pwr
}
V 45800 44700 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 45675 44725 45925 44725 3 0 0 0 -1 -1
L 45675 44675 45925 44675 3 0 0 0 -1 -1
T 46200 44550 5 10 0 1 0 0 1
value=DC 1V
]
{
T 46200 44750 5 10 1 1 0 0 1
refdes=Vdac
T 46200 44550 5 10 1 1 0 0 1
value=DC 2V AC 1
}
N 45800 45300 45800 46000 4
{
T 45300 45600 5 10 1 1 0 0 1
netname=vdac
}
N 48200 46000 48700 46000 4
{
T 48800 46000 5 10 1 1 0 0 1
netname=hk
}
C 48100 44300 1 0 0 EMBEDDEDvpulse-1.sym
[
T 48800 44950 8 10 0 1 0 0 1
refdes=V?
T 48800 45150 5 10 0 0 0 0 1
device=vpulse
T 48800 45350 5 10 0 0 0 0 1
footprint=none
T 48800 45550 5 10 0 0 0 0 1
numslots=0
T 48800 45750 5 10 0 0 0 0 1
description=pulse power source, generator
P 48400 45500 48400 45200 1 0 0
{
T 48450 45300 5 8 1 1 0 0 1
pinnumber=1
T 48450 45300 5 8 0 1 0 2 1
pinseq=1
T 48400 45150 9 8 1 1 0 5 1
pinlabel=+
T 48400 45000 5 8 0 1 0 5 1
pintype=pwr
}
P 48400 44300 48400 44600 1 0 0
{
T 48450 44400 5 8 1 1 0 0 1
pinnumber=2
T 48450 44400 5 8 0 1 0 2 1
pinseq=2
T 48400 44650 9 8 1 1 0 3 1
pinlabel=-
T 48400 44800 5 8 0 1 0 3 1
pintype=pwr
}
V 48400 44900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 48800 44750 5 10 0 1 0 0 1
value=pulse 0 1 10n 10n 100n 1u 2u
T 48800 44550 5 10 0 1 0 0 1
comment=syntax: pulse v1 v2 td tr tf pw per
L 48475 44975 48325 44975 3 0 0 0 -1 -1
L 48475 44975 48475 44825 3 0 0 0 -1 -1
L 48475 44825 48600 44825 3 0 0 0 -1 -1
L 48325 44975 48325 44825 3 0 0 0 -1 -1
L 48325 44825 48200 44825 3 0 0 0 -1 -1
]
{
T 48800 44950 5 10 1 1 0 0 1
refdes=Ihk
T 48800 44750 5 10 1 1 0 0 1
value=pulse 0 1mA 100u 10n 10n 100u
T 48100 44300 5 10 0 0 0 0 1
spice-prototype=I? %pinseq value@
}
C 48300 44000 1 0 0 EMBEDDEDgnd-1.sym
[
P 48400 44100 48400 44300 1 0 1
{
T 48458 44161 5 4 0 1 0 0 1
pinnumber=1
T 48458 44161 5 4 0 0 0 0 1
pinseq=1
T 48458 44161 5 4 0 1 0 0 1
pinlabel=1
T 48458 44161 5 4 0 1 0 0 1
pintype=pwr
}
L 48300 44100 48500 44100 3 0 0 0 -1 -1
L 48355 44050 48445 44050 3 0 0 0 -1 -1
L 48380 44010 48420 44010 3 0 0 0 -1 -1
T 48600 44050 8 10 0 0 0 0 1
net=GND:1
]
N 48400 45500 48400 46000 4
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>=20
> The only question is, how many legacy schematics would you break?
If no spice-prototype is given, spice-noqsi chooses a default based on =
device. The defaults imitate the corresponding code blobs in spice-sdb. =
The result is that my legacy spice-sdb schematics work fine.
> IMO, I don't think that many folks keep gEDA simulations going for
> years and years. And those who do are very clueful and will know how
> to fix their spice schematics using grep and other tools. Therefore,
> breaking legacy work is probably not a show stopper.
>=20
> I say, go for it.
>=20
> Stuart
> Original spice-sdb developer.
>=20
John Doty Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd AT noqsi DOT com
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