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Date: | Wed, 16 Jul 2014 11:08:01 +0100 |
From: | "Peter C.J. Clifton" <pcjc2 AT cam DOT ac DOT uk> |
To: | geda-user AT delorie DOT com |
Cc: | Bernd Walter <ticso AT cicely7 DOT cicely DOT de> |
Subject: | Re: [geda-user] opper ring flag for vias and pins |
In-Reply-To: | <20140715185832.GA56618@cicely7.cicely.de> |
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On 2014-07-15 19:58, Bernd Walter wrote: > On Tue, Jul 15, 2014 at 10:59:07AM -0700, Dave Curtis wrote: >> On 07/15/2014 10:33 AM, Bernd Walter wrote: >> >Because I just remember this, while I wrote about holes and multilayer. >> >I would love to selectively switch of the copper ring per layer on >> >vias and pins. >> >The reason is that I only need to ring on solder side and on connecting >> >layers. >> >On layers I don't need the ring it just reduces space, especially >> >problematic with a via field e.g. inside a BGA. >> >It is not just routing space - the wider space between vias and pins >> >are preferable for groundplanes too. >> > >> So one thing I thought of that might help: >> Set the pad diameter on the Pin[] to the small diameter that you want >> on >> the inner layers. Larger pads cans be had on comp and solder side by >> drawing coincident Pad[] elements with the same pin number. > > This could work as a hack for most cases. > But there are oviously some drawbacks. You need to be able to remove inner layer pad annuli completely for signal integrity reasons on some high-speed lines.
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