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Mail Archives: geda-user/2014/07/15/13:59:23

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Date: Tue, 15 Jul 2014 10:59:07 -0700
From: Dave Curtis <davecurtis AT sonic DOT net>
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To: geda-user AT delorie DOT com
Subject: Re: [geda-user] opper ring flag for vias and pins
References: <20140715173322 DOT GC56151 AT cicely7 DOT cicely DOT de>
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Reply-To: geda-user AT delorie DOT com

On 07/15/2014 10:33 AM, Bernd Walter wrote:
> Because I just remember this, while I wrote about holes and multilayer.
> I would love to selectively switch of the copper ring per layer on
> vias and pins.
> The reason is that I only need to ring on solder side and on connecting
> layers.
> On layers I don't need the ring it just reduces space, especially
> problematic with a via field e.g. inside a BGA.
> It is not just routing space - the wider space between vias and pins
> are preferable for groundplanes too.
>
So one thing I thought of that might help:
Set the pad diameter on the Pin[] to the small diameter that you want on 
the inner layers.  Larger pads cans be had on comp and solder side by 
drawing coincident Pad[] elements with the same pin number.

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