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Date:	Sun, 6 Jul 2014 01:16:31 -0400
Message-Id:	<201407060516.s665GVb3027395@envy.delorie.com>
From:	DJ Delorie <dj AT delorie DOT com>
To:	geda-user AT delorie DOT com
In-reply-to:	<53B8CC66.2080909@sonic.net> (message from Dave Curtis on Sat, 05
	Jul 2014 21:11:18 -0700)
Subject:	Re: [geda-user] pour clearing around pads
References:	<53B8CC66 DOT 2080909 AT sonic DOT net>
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> The peninsulas neck down to less than the minimum copper width rule.

I typically expand the pad clearances until such necks vanish.

> So, first off, I'm surprised that the Cu polygon allows Cu to pour into 
> a space less than the minimum width rule.

Polygon pours are handled poorly in pcb.

> Secondly, I'm wondering if fab houses might flag that as a DRC violation 
> even if pcb doesn't.

Some might.  I've had one break loose and cause a short in a
manufactured board before, so I'm particularly wary of them.

> Third, is it legal to specify zero-width Pad[] elements in a footprint, 
> and assign clearance values, in order to composite some clearance into 
> the footprint?

I think this is fine, although perhaps a tiny non-zero width might be
needed.  I don't know if these cause outputs in the gerber file,
though, so be careful.

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