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Date:	Sat, 05 Jul 2014 21:11:18 -0700
From:	Dave Curtis <davecurtis AT sonic DOT net>
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To:	geda-user AT delorie DOT com
Subject:	[geda-user] pour clearing around pads
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This is a multi-part message in MIME format.
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I'm working on a footprint where if I follow the data-sheet geometry and 
my normal design rules, I end up with a footprint where very skinny 
copper peninsulas sneak between pads when it is placed in a polygon.  
The peninsulas neck down to less than the minimum copper width rule.

So, first off, I'm surprised that the Cu polygon allows Cu to pour into 
a space less than the minimum width rule.

Secondly, I'm wondering if fab houses might flag that as a DRC violation 
even if pcb doesn't.

Third, is it legal to specify zero-width Pad[] elements in a footprint, 
and assign clearance values, in order to composite some clearance into 
the footprint? Or is pcb going to get cranky if a Pad[] is zero width? I 
could imagine it would be hard to connect to... so I guess it needs to 
share a pin number with something else.

footprint work-in-progress attached.



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