Mail Archives: geda-user/2013/10/27/15:08:31
On Sun, 2013-10-27 at 22:09 +0430, James Jackson wrote:
> Sorry for three emails in a row; just trying to make myself clear.
>
>
> I've now run a test where I had a master schematic which included two
> subcircuits. Each cubcircuit consisted simply of a resistor, with each
> pin connected to a generic-power (nets = vcc:1 and gnd:1).
>
>
> Running this through gsch2pcb results in two resistors on the PCB, but
> indeed the two power nets are not connected between the subcircuits.
> In the Netlist dialog, again each subcircuit has its own Vcc / Gnd
> nets.
>
>
> I'd welcome advice on how to merge nets in this situation - I'd rather
> not run power lines to each sub circuit explicitly as this will
> significantly clutter up my master schematic.
I think you can only turn hierarchy prefixing on/off for net-names on a
global basis. It will be all or nothing. (Netnames share one common
name-space, OR, they will get prefixed by their hierarchy paths).
Do you _need_ hierarchy, would a multi-page set of flat schematics be
better?
IMO, not explicitly calling out the power connections is a mistake, just
like using symbol embedded (hidden) power-nets on components is.
If you want to avoid clutter on your schematics, you can shunt the
connections onto a separate page in the sub-schematics, BUT, I don't
think you can do that when instancing the hierarchy.
I "might" be wrong though, and _perhaps_ you can split the sub-circuit
symbol into multiple pieces when instantiating the sub-circuit, but
again - I don't think that is a wise thing to do - even if it happened
to work.
FWIW, if you're targeting board layout, PCB doesn't really support
hierarchy. It treats the hierarchical names and net-names as flat.
What is it exactly you're trying to achieve with hierarchy?
Best regards,
--
Peter Clifton <peter DOT clifton AT clifton-electronics DOT co DOT uk>
Clifton Electronics
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