Mail Archives: geda-user/2013/10/27/14:41:16
On Sun, 2013-10-27 at 21:04 +0430, James Jackson wrote:
> Hi all,
>
>
> Many thanks for this - I've now got a fairly hefty multi-page
> schematic drawn up (using the source=x attribute to link subcircuits
> to a master sheet with the signal routes between subcircuits), with a
> separate schematic for power rails.
>
>
> I now have a problem when I run gsch2pcb - the 'split' ICs with the
> same refdes (i.e. power in subcircuit 1 (refdes SS1), signal in
> subcircuit 2 (refdes SS2)) are being placed twice on my PCB, with
> names SS1/U1 and SS2/U1.
>
>
> How can I force gsch2pcb to 'do the right thing' here?
The simple answer is I you cannot.
If you are using a true hierarchy, then it must be separate components
in each piece, and each piece must be identical. slot=... attributes
would need to be identical as well.
If you actually have two different sub-circuits, then you could turn off
hierarchical naming, but I think that defeats the point.
One final option - export connections to the chip you wish to share, and
place that chip on the parent level of hierarchy.
Regards,
--
Peter Clifton <peter DOT clifton AT clifton-electronics DOT co DOT uk>
Clifton Electronics
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