Mail Archives: geda-user/2012/02/20/01:21:35
> I suppose the "=" (blocking) makes the code sequential,
NOT SEQUENTIAL. Think "series wired". "=" means "if the signal has
been re-defined by some previous logic, use that new output'd signal
as my input". "<=" means "my inputs will always be the original
signals."
Remember, verilog is a SCHEMATIC. It is NOT CODE. It is wires and
gates and latches. If you had a gschem page with wires and gates and
latches, you wouldn't expect each gate's output to be computed
sequentially, would you?
> but what the heck does the synthesis tool build?
the synthesis tool will probably create a circuit of combinatoric
gates connected in series to perform the logic you asked for.
I think it builds the same logic either way, the big difference is
when the value becomes valid relative to other signals. If you're
using "=" you're going to be using the output of the combinatorics
directly, so you get some arbitrary propogation delay, which may cause
problems. With "<=" it's delayed a clock, but the edges happen in
sync with all the other edges.
The problem with propogation delay, is you might not meet the setup
times for whoever uses those values. At high clock speeds, you need
the latches to re-synchronize everything and reset the setup times vs
propogation delays.
> Wouldn't your method of 'previous count' and 'count' use twice as many
> registers?
Don't confuse verilog "registers" with hardware "latches". Registers
are just "values you can change" but they could easily be the output
of a NAND gate or even just a wire, not always a physical latch.
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