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Date:	Mon, 20 Feb 2012 07:02:52 +0100
From:	Peter Stuge <peter AT stuge DOT se>
To:	geda-user AT delorie DOT com
Subject:	Re: [geda-user] verilog question - blocking/non-blocking
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DJ Delorie wrote:
> > Question : does one method synthesize significantly different logic
> > than the other?
> 
> For those who think verilog is software, it's not...
..
> If you think software-like, think of your code this way:

It might be worth emphasizing that logic is not sequential the way
software is.

If you can visualize easily, then think of your lines of logic design
running "down" in a file being "rotated" into "executing" in hardware
almost completely in parallell; ie. simultaneously.

This is an oversimplification, but key when starting out is to wrap
head around that even though you write things sequentially they may
happen simultaneously in running logic.

Enter good friend finite state machine. The two counter assignments
both support state machines, but as was pointed out with slightly
different behavior to keep in mind, and design around. That's the
almost in "almost completely in parallell." ;)


//Peter

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