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Message-ID:	<5087F3AF.6050706@laserlinc.com>
Date:	Wed, 24 Oct 2012 09:57:03 -0400
From:	Joshua Lansford <Joshua DOT Lansford AT laserlinc DOT com>
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To:	geda-user AT delorie DOT com
Subject:	[geda-user] XilinxPinChecker
Reply-To:	geda-user AT delorie DOT com

Hey guys, here is another script someone else might find useful.  It is 
used to cross check the pin assignments between a Xilinx FPGA/CPLD in a 
schematic and in the UCF file used by the Xilinx tool software.
http://public.laserlinc.com/Joshua/checkXilinxPins.py

First you have to generate a pads netlist from your schematics using 
gnetlist

gnetlist -g pads sheet*.sch -o netlist.ASC

Then you call the tool and pass a reference to the ucf as well as the 
netlist.  You also need to specify the refdes of the Xilinx part being 
checked.

./checkXilinxPins.py xilinxConstraintsFile.ucf netlist.ASC --refdes U6

The UCF file itself needs to be annotated with the expected schematic 
netnames of the signals.
#quad SPI
NET "SPI_CS_n_Output"        LOC = T5   | IOSTANDARD = LVCMOS33;         
              #schematic Flash_CS_L
NET "SPI_SCK_Output"         LOC = Y21  | IOSTANDARD = LVCMOS33;     
               #schematic Flash_SCK
NET "SPI_MOSI_MISO0_Output"  LOC = AB20 | IOSTANDARD = LVCMOS33;  # also 
(MISO0)    #schematic Flash_SI_IO0
NET "SPI_MISO_MISO1_Input"   LOC = AA20 | IOSTANDARD = LVCMOS33;  # also 
(MISO1)    #schematic Flash_SO_IO1
NET "SPI_Wn_MISO2_Output"    LOC = U14  | IOSTANDARD = LVCMOS33;# also 
(MISO2)      #schematic Flash_WP_L_IO2
NET "SPI_HOLDn_MISO3_Output" LOC = U13  | PULLUP | IOSTANDARD = 
LVCMOS33; # (MISO3) #schematic Flash_HOLD_L_IO3

The script is hard wired to ignore different power and ground schematic 
names which can be added to.
If you have a UCF signal that the tool should ignore give it a schematic 
name which includes IgnoreCheck
~Joshua

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