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From:	"Charles Sandmann" <cwsdpmi AT earthlink DOT net>
Newsgroups:	comp.os.msdos.djgpp
References:	<89da6560807291624he0cb2d1u696542e552887e8d AT mail DOT gmail DOT com>
Subject:	Re: djgpp v2 : Control register access segfaults
Date:	Mon, 4 Aug 2008 23:18:56 -0500
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To:	djgpp AT delorie DOT com
DJ-Gateway:	from newsgroup comp.os.msdos.djgpp
Reply-To:	djgpp AT delorie DOT com

Lael Jones" <lael DOT jones AT gmail DOT com> wrote in message 
news:89da6560807291624he0cb2d1u696542e552887e8d AT mail DOT gmail DOT com...

>I'm upgrading my application from djgpp v1 to djgpp v2 and am seeing a seg 
>fault in the debug build when the application tries to access (read or 
> >write) control registers (specifically CR4).  The inline assembly I am 
>using is:

>   // Enable SSE instructions via OSFXSR (bit 9 of CR4).
> The seg fault always occurs on "movl %%cr4, %%eax".
> Are there any known issues/changes to djgpp that would cause this?

As mentioned elsewhere, djgpp v1's go32 ran at ring 0 in non-dpmi 
environments.   The default cwsdpmi runs at ring 3.  cwsdpr0 can run at ring 
0 if that's needed, as can pmode and some other dpmi providers.

I've also been convinced to update both r5 and r6 of cwsdpmi to 
automatically set the OSFXSR bit (and update contact info) - if you or 
anyone else wants to test the updates before release send me an email. 

- Raw text -