From:	"Joel_S" <jbs30000 DOT news DOT invalid AT web2news DOT net>
Newsgroups:	comp.os.msdos.djgpp
Subject:	Re: C/C++ versions of asm opcodes.
Date:	Thu, 23 Jan 2003 02:27:05 +0100
Organization:	Web2news.com
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To:	djgpp AT delorie DOT com
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Reply-To:	djgpp AT delorie DOT com

Hey, you forgot SHLD/SHRD :)
No, but seriously, I don't need it.  Thanks for the code that you
already provided.

> There are also RCL and RCR, which would need the Rotate
> and Shift operations
> I gave to also have a carry flag. RCL and RCR are useful
> when you want to
> rotate values of more than 32 bits by 1 bit at a time.
> Otherwise, I don't
> know why Intel allowed RCL and RCR to have shift amounts
> of more than 1 bit.
> Maybe they just wanted to give RCL/RCR equal footing to the other
> shift/rotate operations.
>
> unsigned long rcl (unsigned long src, unsigned long samt,
> int *carry){
>     unsigned long dst;
>     samt &= 31;
>     if (samt == 0){
>         dst = src;
>     } else {
>         dst = (src << samt) | (src >> (33 - samt)) |
> (carry ? (1 << (samt -
> 1)) : 0);
>         carry = src & (1 << (32 - samt));
>     }
>     return dst;
> }
>
> unsigned long rcr (unsigned long src, unsigned long samt,
> int *carry){
>     unsigned long dst;
>     samt &= 31;
>     if (samt == 0){
>         dst = src;
>     } else {
>         dst = (src >> samt) | (src << (33 - samt)) |
> (carry ? (1 << (32 -
> samt)) : 0);
>         carry = src & (1 << (samt - 1));
>     }
>     return dst;
> }

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