From:	sandmann AT clio DOT rice DOT edu (Charles Sandmann)
Message-Id:	<10210111450.AA21575@clio.rice.edu>
Subject:	Re: Int 0x22???
To:	mdsisco AT qtiworld DOT com (Sisco, Michael)
Date:	Fri, 11 Oct 2002 09:50:37 -0500 (CDT)
Cc:	djgpp AT delorie DOT com
In-Reply-To:	<BDD73AE8AEE3EF438E07420C2600E9F65C9194@qtiexch0.qgraph.com> from "Sisco, Michael" at Oct 11, 2002 09:16:49 AM
X-Mailer:	ELM [version 2.5 PL2]
Mime-Version:	1.0
Reply-To:	djgpp AT delorie DOT com
Errors-To:	nobody AT delorie DOT com
X-Mailing-List:	djgpp AT delorie DOT com
X-Unsubscribes-To:	listserv AT delorie DOT com

> > > Doesn't the interrupt controller prevent "simultaneous" interrupts
> > > anyway?
> > 
> > This happens after you send the EOI to the controller.  There are
> > several dozen instructions that need to be executed before you get
> > out of your routine (and the wrapper) after the STI happens.  If a
> > second interrupt is pending then it would immediately trigger. 
>
> Isn't this the case even if I don't disable/enable? I'm still 
> sending the EOI to the controller. What keeps it from issuing the next
> interrupt in this case? 

The interrupt handler is started with interrupts disabled (it's the way
interrupt handlers are typically configured).  They will stay disabled
until an STI is issued, or the IRET reenables them.  In general you
don't need (or want) to issue an STI (enable) unless you want nested
interrupts.

> Is this something specific to using the interrupt wrappers?

No.  If the interrupt handler is written directly in assembler it's
the same thing.

> I've seen many examples of interrupt handlers (not DJGPP/DPMI) that 
> start with disable() and end with enable(). What's different here?

I'm not sure where the disable/enable stuff came from; it's usually
in old TCC/BCC or MSC code.  I'm not sure if this is some mis-feature
of thier wrappers, or some bad example code too widely copied.

- Raw text -