Mail Archives: djgpp/1997/07/19/04:02:45
On Mon, 14 Jul 1997 14:36:50 +0200, Johan Karlsson <k AT sm DOT luth DOT se> wrote:
>Peter Steiner wrote:
>>
>> On Wed, 9 Jul 1997 08:20:16 GMT, Eli Zaretskii <eliz AT is DOT elta DOT co DOT il> wrote:
>>
>> >Only in the CMOS setup of your machine, if your setup has such an option.
>>
>> There is a way to disable caching through the page-table
>> Setting bit 3=1 disables write-back and
>> setting bit 4=1 disables caching
>> I don't recommend using this since the chipset normally will take care of
>> it for you.
>
>What I realy would like to do is disabling the cache for a specific
>memory area, either by physical address or linear address returned from
>__dpmi_physical_address_mapping.
These bits exist in each Page-Table-Entry so you can switch the cache for
each page (4-kB-block) separately (if you get access to the Page-Table).
Paul Dixon posted a complete description to this thread so I quit here.
Bye,
Peter Steiner
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