Mail Archives: djgpp/1997/03/21/08:40:44
Once upon a time (on 20 Mar 97 at 14:55) Anthony Q. Bachler said:
> Try clearing the interupt enable bit of the MSW as one of the first steps in
> the ISR. This will cause the hardware to store any interupts that occur and
> execute them when you reenable them. To disable them use the CLI assembly
> instruction. To reenable them use the STI instruction. A word of caution,
> STI should be immediately followed by an IRET to prevent the problem you are
> experienceing. The problem you are having is that the stack is being
> corrupted. When you perform an STI, the processor should hold off executing
> any pending interupts until after the next command. I know for a fact that
> it works this way on the 8086-80686. On a different processor, it may work
> differently. The above details are for the intel CPU's, but the method is
> the same for most others.
This won't work under many DPMI servers (as well as under many, perhaps all,
multitasking environments - WinNT, Linux/DOSEMU, OS/2, OpenDOS MultiTasker) -
they virtualize the interrupts and STI & CLI instructions are emulated by the
underlying software. They have effect only on the current application/VM.
Several days ago I've posted to this newsgroup a short proggy which makes the
interrupts reentrant. Subject: line of the thread had an ISR string in it -
browse mail archives on http://www.delorie.com/djgpp/ and you should be able
to find the message. If not then e-mail me privately and I'll send you the
code.
---------- Visit http://ananke.amu.edu.pl/~grendel ------------
You're just a waste of time, you're just a babbling face, you're
just three sick holes that run like sores, you're fucking waste
you're like a slug on the floor, oh you're usless and ugly and
useless and ugly, and shiver and shake when I think of how you
make me hate.
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