Mail Archives: djgpp/1997/03/20/11:39:42
In article <332c1c1c DOT 1840126 AT ursa DOT smsu DOT edu>, Tony O'Bryan
<aho450s AT nic DOT smsu DOT edu> writes
>In protected mode, the default register and word size are 32-bits. In real
>mode, both are 16-bits. The '386+ processors use the same code sequence to
>represent ax and eax. They also use the exact same code for 32-bit overrides
>(from real mode) and 16-bit overrides (from protected mode). So to access a
>16-bit memory address using ax from protected mode, an operand-size override is
>needed. This override is 1 byte (66h) long and is included in the processor
>prefetch cycle. It causes a delay from the processor's perspective (given that
>the processor can see delays 1 nanosecond long *grin*), but won't cause an
>appreciable delay for the user.
Wrong for a Pentium, which treats the prefix as a 1 clock unpairable
instruction. In the worst case (consecutive simple prefixed ops) this
can cause a 4* speed reduction!
The real problem is more subtle. gcc is inherently a 32 bit compiler,
and seems to have real problems understanding 'short's. It will
frequently generate code to set the upper half of registers even though
you and I know it makes no difference to the result!
---
Paul Shirley: shuffle chocolat before foobar for my real email address
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