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Mail Archives: djgpp/1996/12/22/15:40:28

From: elf AT netcom DOT com (Marc Singer)
Message-Id: <199612222018.MAA00530@netcom4.netcom.com>
Subject: Re: MMX
To: chambersb AT juno DOT com (Benjamin D Chambers)
Date: Sun, 22 Dec 1996 12:18:43 -0800 (PST)
Cc: djgpp AT delorie DOT com (DJGPP List Alias)
In-Reply-To: <19961221.171924.8327.4.chambersb@juno.com> from "Benjamin D Chambers" at Dec 20, 96 08:15:45 pm
MIME-Version: 1.0

> I saw a lot of posts about Intel MMX.
> What is it?

The gap between real-time, real-media applications (MPEG, animation,
audio) and the current generation of hardware is starting to close.
CPU throughput has risen such that we can do MPEG playback in
real-time on affordable hardware.  Compression, however, is still just
out of reach.  The gap is slightly smaller for some other animation
and audio algorithms.  Intel (and DEC) are introducing CPUs with
instructions aimed at performing SIMD operations, Single Instruction
Multiple Data.  Intel's instructions appear to be somewhat more
general purpose.  Thus, if we can process eight pixels or eight audio
samples in one instruction (64 bit registers required here) you should
be able to imagine the performance improvement.

Intel made a big booboo by attempting to economize on these special
registers by requiring a special CPU to use MMX instructions.  This
mode switch is slow and it is incompatible with floating point
operations since MMX uses the same register stack as the floating
point operations.  It is turing into a pretty big bungle since it is
not possible to upgrade-and-go without patching the operating system.

DEC was somewhat smarter in that they use the normal registers.  The
new instructions are (I believe) slated for the 21264 CPU due out at
the end of 1997 (I think).  The claim is that this chip will be able
to compress MPEG video *in*real*time*, 30 frames per second.  They
have the advantage over Intel in two ways: 1) they don't have to
support the 8086 legacy which is a relentless hassle for many many
many reasons, and 2) all of the 21x6x chips sport all 64 bit registers
and instructions.  In spite of their grievously inept marketing
department, the DEC engineers show skill and foresight that Intel (as
well as our Redmond pals) can't seem to buy.

-- Marc Singer

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