From:	nxk3 AT b63526 DOT student DOT cwru DOT edu (Natarajan Krishnaswami)
Newsgroups:	comp.os.msdos.djgpp
Subject:	Re: Optimization
Date:	2 Dec 1996 04:04:57 GMT
Organization:	Case Western Reserve University, Cleveland OH (USA)
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In article <57nsm0$cvp AT lyra DOT csx DOT cam DOT ac DOT uk>, G.P. Tootell wrote:
> ok. i'm confused now. i thought the cache was 32 bytes but 128 bits
> is 16 bytes no? so just how big is the cache :) or did it change
> between the 486 and pentium?

1) 128 bits is indeed 16 bytes. :)
2) The cache is 8k on a 486, and I believe the caches (I and D) are
   each 8k on the Pentium, though I may be mistaken.
3) The size of a cache line did change:

    "The data and instruction caches hold 8K bytes each. The cache line
    width of the Pentium processor is 256 bits or 32 bytes. A line can be
    filled from memory with a four-transfer burst cycle. External caches
    are not likely to use cache lines smaller than those of the internal
    cache.
    
    "Cache lines can only be mapped to 32-byte aligned blocks of main
    memory. (A 32-byte aligned block begins at an address which is clear
    in its low-order five bits.) The caches do not support
    partially-filled cache lines, so caching even a single doubleword
    requires caching an entire line."

(Pentium (R) Processor Family Developer's Manual, Volume 3: Architecture
and Programming Manual,  page 18-1)


For those interested, I got this datasheet (PDF) from Intel at
http://www.intel.com/design/product.htm


Enjoy,
Natarajan

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