From:	Kevin AT Quitt DOT net (Kevin D. Quitt)
Newsgroups:	comp.os.msdos.djgpp
Subject:	Re: Optimization
Date:	Sun, 01 Dec 1996 17:05:07 GMT
Organization:	Cruisin' from home
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On 29 Nov 1996 23:47:12 GMT, gpt20 AT thor DOT cam DOT ac DOT uk (G.P. Tootell) wrote:
>ok. i'm confused now. i thought the cache was 32 bytes but 128 bits is 16 bytes
>no? so just how big is the cache :) or did it change between the 486 and pentium?

The cache reads 4 words of 32 bits in each load.  The idea is to already have
what you're probably going to need next 75% of the time, rather than having it
there in case you need it again.  The P6 instruction cache, for example, is
sensitive to the instructions therein and will prefetch from both possible
targets of a conditional jump (before the instruction even gets to the
processor).  That's why absolute and conditional jumps are now considered to
take zero cycles on advanced processors like the P6 and 68060.

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