From:	vecna AT engin DOT umich DOT edu (Jimmy Wan)
Newsgroups:	comp.os.msdos.djgpp
Subject:	Re: Optimization : OFF-TOPIC!
Date:	Sun, 01 Dec 96 17:16:30 GMT
Organization:	University of Michigan
Lines:	14
Message-ID:	<57seln$ivp@lastactionhero.rs.itd.umich.edu>
References:	<57hg9b$or5 AT kannews DOT ca DOT newbridge DOT com> <329C95AD DOT C3E AT silo DOT csci DOT unt DOT edu> <57k531$5bu AT kannews DOT ca DOT newbridge DOT com> <slrn59ubiq DOT nb DOT nxk3 AT b63526 DOT student DOT cwru DOT edu> <57nsm0$cvp AT lyra DOT csx DOT cam DOT ac DOT uk> <32b1ba0f DOT 58325187 AT news DOT pacificnet DOT net>
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DJ-Gateway:	from newsgroup comp.os.msdos.djgpp

In article <32b1ba0f DOT 58325187 AT news DOT pacificnet DOT net>, Kevin AT Quitt DOT net wrote:
>The P6 instruction cache, for example, is sensitive to the instructions
>therein and will prefetch from both possible targets of a conditional 
>jump (before the instruction even gets to the processor).  That's why
>absolute and conditional jumps are now considered to take zero
>cycles on advanced processors like the P6 and 68060.

I know this is off-topic, but I can't help it.  Anyone know if the
P6 implements branch folding?  I didn't think it did, but from the
sounds of your post, it does.

Jimmy Wan               University of Michigan-Computer Engineering
Turtle Beach Maui Page  http://www-personal.umich.edu/~vecna/maui.html
Device Driver Page	http://www-personal.umich.edu/~vecna/drivers.html

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