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Mail Archives: djgpp/1996/09/18/17:11:23

From: Mihai Moise <moisemih AT ift DOT ulaval DOT ca>
Newsgroups: comp.os.msdos.djgpp
Subject: Re: Quick inline asm question...
Date: Wed, 18 Sep 1996 12:14:40 -0400
Organization: Universite Laval
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Message-ID: <32401FF0.41C67EA6@ift.ulaval.ca>
References: <51mrb2$o5f AT news DOT cais DOT com> <323F61CD DOT 797B AT cs DOT com>
NNTP-Posting-Host: britten.ift.ulaval.ca
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To: djgpp AT delorie DOT com
DJ-Gateway: from newsgroup comp.os.msdos.djgpp

John M. Aldrich wrote:
> 
> David Charlton wrote:

> Well, in as much as I understand 16 vs 32-bit assembly, the 'e*x'
> registers
> are simply 32-bit extended versions of the '*x' registers.  So, %%ax is
> in
> actuality the lower 16 bits of %%eax.  What you are trying to do is add
> the register to itself, which I doubt will work.
> 

Actually, adding a register to itself just might work. But intel
provides no opcodes to mix 16-bit and 32-bit registers in an
instruction. Besides, even if such opcodes existed, the resulting
algorithm would not be portable.

Mihai
Check out the DOs port of svgalib at
http://wwwbacc.ift.ulaval.ca/~moisemih

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