Date:	Thu, 22 Jul 1999 10:55:04 +0300 (IDT)
From:	Eli Zaretskii <eliz AT is DOT elta DOT co DOT il>
X-Sender:	eliz AT is
To:	Nate Eldredge <nate AT cartsys DOT com>
cc:	djgpp-workers AT delorie DOT com
Subject:	Re: .align directives in libc.a
In-Reply-To:	<37969AA1.2B135315@cartsys.com>
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Reply-To:	djgpp-workers AT delorie DOT com
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On Wed, 21 Jul 1999, Nate Eldredge wrote:

> Eli Zaretskii wrote:
> > It would be nice if we could finally close this issue
> > for good, at least until Intel come out with a chip that fetches on
> > 32-byte boundary ;-)
> 
> My AMD K6-3 has 32 byte cache lines (and I think the K6-2 did as
> well)...

And the same is true for the Pentium family.

However, the prefetch queues fetch on 16-byte boundaries, so 16-byte
alignment is as good as 32-byte, speedwise.  In fact, Intel manuals
recommend to use the equivalent of ".balign 16,,7" for function entry
points and targets of jump instructions.  Unfortunately, Andris says
that it's not simple to make GCC use anything but ".align N" in the
code it emits.  So we'll probably have to live with some waste, for a
while.

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