Checking patch sysdeps/x86/cpu-features.c...
error: while searching for:
  unsigned int stepping = 0;
  enum cpu_features_kind kind;

#if !HAS_CPUID
  if (__get_cpuid_max (0, 0) == 0)
    {

error: patch failed: sysdeps/x86/cpu-features.c:635
error: sysdeps/x86/cpu-features.c: patch does not apply
Checking patch sysdeps/x86/dl-cacheinfo.h...
error: while searching for:
  cpu_features->level3_cache_linesize = level3_cache_linesize;
  cpu_features->level4_cache_size = level4_cache_size;

  /* The default setting for the non_temporal threshold is 1/4 of size
     of the chip's cache. For most Intel and AMD processors with an
     initial release date between 2017 and 2023, a thread's typical
     share of the cache is from 18-64MB. Using the 1/4 L3 is meant to
     estimate the point where non-temporal stores begin outcompeting
     REP MOVSB. As well the point where the fact that non-temporal
     stores are forced back to main memory would already occurred to the
     majority of the lines in the copy. Note, concerns about the
     entire L3 cache being evicted by the copy are mostly alleviated
     by the fact that modern HW detects streaming patterns and
     provides proper LRU hints so that the maximum thrashing
     capped at 1/associativity. */
  unsigned long int non_temporal_threshold = shared / 4;
  /* If no ERMS, we use the per-thread L3 chunking. Normal cacheable stores run
     a higher risk of actually thrashing the cache as they don't have a HW LRU
     hint. As well, there performance in highly parallel situations is

error: patch failed: sysdeps/x86/dl-cacheinfo.h:738
error: sysdeps/x86/dl-cacheinfo.h: patch does not apply
Checking patch sysdeps/x86/include/cpu-features.h...
Hunk #1 succeeded at 946 (offset 31 lines).