From patchwork Mon Oct 20 15:50:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Zihong X-Patchwork-Id: 122287 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C26713858407 for ; Mon, 20 Oct 2025 15:53:31 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTPS id 62D7E3858C62 for ; Mon, 20 Oct 2025 15:52:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 62D7E3858C62 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 62D7E3858C62 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1760975555; cv=none; b=MIaKOI5dxujVmrQx9nM3oaaG4/zfQ4EDkIFKmslnVMRhpqyjZCiPEQ84N+ZuMMRRwESoFuVJYkH6H/2Lb58DnFTHnvu3Sw3oMVf2hdVqo6W44vk4ErhQkLkq+5qSXZGbFyL4wmsuzwfh1iLvSYoXm6xNhQnccMZ3fcwCKeJXTNY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1760975555; c=relaxed/simple; bh=Gaqx+HIL4ZIGk6fc7uhZcQgmSUu2gsZxcEB0qmj4Iv8=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=jSurxA2QAdU08xunjZMZi6tuo4GWlesFbx83oHYxebcgsp2Iyl51rpe1Wcc32Hz5AJ4HUDGuOJSQuRIHlhLrPqtSLOc/Pr1ZPLe1XI2wvJ0EYMp3sqzn0A9W4KJeWIGFT10FLVI4uX+UE+D8wB0mYzfJHmGOD/q4Pb0amSxuL2M= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from Mobilestation.localdomain (unknown [183.6.59.216]) by APP-01 (Coremail) with SMTP id qwCowAC3EaRwWvZoOCsdEg--.25622S4; Mon, 20 Oct 2025 23:51:22 +0800 (CST) From: Yao Zihong To: libc-alpha@sourceware.org Cc: adhemerval.zanella@linaro.org, andrew@sifive.com, schwab@linux-m68k.org, bergner@linux.ibm.com, jlaw@ventanamicro.com, palmer@dabbelt.com, vineetg@rivosinc.com, jerry.shih@sifive.com, zhangyin2018@iscas.ac.cn, zihong.plct@isrc.iscas.ac.cn, zihongyao@outlook.com, Dai Chengrong Subject: [PATCH v1 2/2] riscv: Skip RVV build when assembler lacks vector support Date: Mon, 20 Oct 2025 23:50:29 +0800 Message-ID: <20251020155101.83064-3-zihong.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251020155101.83064-1-zihong.plct@isrc.iscas.ac.cn> References: <20251020155101.83064-1-zihong.plct@isrc.iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAC3EaRwWvZoOCsdEg--.25622S4 X-Coremail-Antispam: 1UD129KBjvJXoW3XrW8Aw15urWkKF17AFyrWFg_yoWxJrWUpF 4Fka45GFZ3Jr1xCrWSkw10gwn5Xr4rWr15A3WFkw4UJayUArWxJFZFyw13tr1DKF95JFWf Zr10gFnFkrZ0v37anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmY14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r4UJwAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67 kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY 6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42 IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIev Ja73UjIFyTuYvjfUF5rcDUUUU X-Originating-IP: [183.6.59.216] X-CM-SenderInfo: p2lk00vjoszunw6l223fol2u1dvotugofq/ X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~patchwork=sourceware.org@sourceware.org This patch integrates assembler feature detection so that RVV objects are skipped entirely when the assembler does not support vector instructions. It avoids build failures on toolchains without RVV support. Co-authored-by: Dai Chengrong Signed-off-by: Yao Zihong --- config.h.in | 3 ++ sysdeps/riscv/configure | 34 +++++++++++++++++++ sysdeps/riscv/configure.ac | 24 +++++++++++++ .../unix/sysv/linux/riscv/multiarch/Makefile | 7 +++- .../linux/riscv/multiarch/ifunc-impl-list.c | 6 ++++ .../unix/sysv/linux/riscv/multiarch/memset.c | 4 +-- 6 files changed, 75 insertions(+), 3 deletions(-) diff --git a/config.h.in b/config.h.in index 5378883060..f8fc16a19f 100644 --- a/config.h.in +++ b/config.h.in @@ -128,6 +128,9 @@ /* RISC-V floating-point ABI for ld.so. */ #undef RISCV_ABI_FLEN +/* Define if assembler supports vector instructions on RISC-V. */ +#undef HAVE_RISCV_ASM_VECTOR_SUPPORT + /* LOONGARCH integer ABI for ld.so. */ #undef LOONGARCH_ABI_GRLEN diff --git a/sysdeps/riscv/configure b/sysdeps/riscv/configure index 3ae4ae3bdb..1d28e82135 100755 --- a/sysdeps/riscv/configure +++ b/sysdeps/riscv/configure @@ -83,3 +83,37 @@ if test "$libc_cv_static_pie_on_riscv" = yes; then fi +# Check if assembler supports attribute riscv vector macro. +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for gcc attribute riscv vector support" >&5 +printf %s "checking for gcc attribute riscv vector support... " >&6; } +if test ${libc_cv_gcc_rvv+y} +then : + printf %s "(cached) " >&6 +else case e in #( + e) cat > conftest.S <&5 \ + 2>&5 ; then + libc_cv_gcc_rvv=yes +fi +rm -f conftest* ;; +esac +fi +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $libc_cv_gcc_rvv" >&5 +printf "%s\n" "$libc_cv_gcc_rvv" >&6; } + +if test x"$libc_cv_gcc_rvv" = xyes; then + printf "%s\n" "#define HAVE_RISCV_ASM_VECTOR_SUPPORT 1" >>confdefs.h + +fi + +config_vars="$config_vars +have-gcc-riscv-rvv = $libc_cv_gcc_rvv" + diff --git a/sysdeps/riscv/configure.ac b/sysdeps/riscv/configure.ac index ee3d1ed014..43b1af09c6 100644 --- a/sysdeps/riscv/configure.ac +++ b/sysdeps/riscv/configure.ac @@ -43,3 +43,27 @@ EOF if test "$libc_cv_static_pie_on_riscv" = yes; then AC_DEFINE(SUPPORT_STATIC_PIE) fi + +# Check if assembler supports attribute riscv vector macro. +AC_CACHE_CHECK([for gcc attribute riscv vector support], + libc_cv_gcc_rvv, [dnl +cat > conftest.S <&AS_MESSAGE_LOG_FD \ + 2>&AS_MESSAGE_LOG_FD ; then + libc_cv_gcc_rvv=yes +fi +rm -f conftest*]) + +if test x"$libc_cv_gcc_rvv" = xyes; then + AC_DEFINE(HAVE_RISCV_ASM_VECTOR_SUPPORT) +fi + +LIBC_CONFIG_VAR([have-gcc-riscv-rvv], [$libc_cv_gcc_rvv]) diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile b/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile index de8024b86d..b629bc1e82 100644 --- a/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile +++ b/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile @@ -5,8 +5,13 @@ sysdep_routines += \ memcpy_noalignment \ memset \ memset-generic \ - memset_vector \ # sysdep_routines +ifeq ($(have-gcc-riscv-rvv),yes) +sysdep_routines += \ + memset_vector \ + # rvv sysdep_routines +endif + CFLAGS-memcpy_noalignment.c += -mno-strict-align endif diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c b/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c index b4defac9c4..e092cbe50f 100644 --- a/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c +++ b/sysdeps/unix/sysv/linux/riscv/multiarch/ifunc-impl-list.c @@ -27,7 +27,9 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, size_t i = max; bool fast_unaligned = false; +#if defined(HAVE_RISCV_ASM_VECTOR_SUPPORT) bool rvv_ext = false; +#endif struct riscv_hwprobe pair = { .key = RISCV_HWPROBE_KEY_CPUPERF_0 }; if (__riscv_hwprobe (&pair, 1, 0, NULL, 0) == 0 @@ -35,10 +37,12 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, == RISCV_HWPROBE_MISALIGNED_FAST) fast_unaligned = true; +#if defined(HAVE_RISCV_ASM_VECTOR_SUPPORT) struct riscv_hwprobe ext_pair = { .key = RISCV_HWPROBE_KEY_IMA_EXT_0 }; if (__riscv_hwprobe (&ext_pair, 1, 0, NULL, 0) == 0 && (ext_pair.value & RISCV_HWPROBE_IMA_V)) rvv_ext = true; +#endif IFUNC_IMPL (i, name, memcpy, IFUNC_IMPL_ADD (array, i, memcpy, fast_unaligned, @@ -46,8 +50,10 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, IFUNC_IMPL_ADD (array, i, memcpy, 1, __memcpy_generic)) IFUNC_IMPL (i, name, memset, +#if defined(HAVE_RISCV_ASM_VECTOR_SUPPORT) IFUNC_IMPL_ADD (array, i, memset, rvv_ext, __memset_vector) +#endif IFUNC_IMPL_ADD (array, i, memset, 1, __memset_generic)) return 0; diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/memset.c b/sysdeps/unix/sysv/linux/riscv/multiarch/memset.c index 8c1362e064..2fdb2e7e07 100644 --- a/sysdeps/unix/sysv/linux/riscv/multiarch/memset.c +++ b/sysdeps/unix/sysv/linux/riscv/multiarch/memset.c @@ -38,11 +38,11 @@ static inline __typeof (__redirect_memset) * select_memset_ifunc (uint64_t dl_hwcap, __riscv_hwprobe_t hwprobe_func) { unsigned long long v; - +#if defined(HAVE_RISCV_ASM_VECTOR_SUPPORT) if (__riscv_hwprobe_one (hwprobe_func, RISCV_HWPROBE_KEY_IMA_EXT_0, &v) == 0 && (v & RISCV_HWPROBE_IMA_V) == RISCV_HWPROBE_IMA_V) return __memset_vector; - +#endif return __memset_generic; }