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Thu, 16 Apr 2026 22:57:59 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: "H.J. Lu" Date: Fri, 17 Apr 2026 13:57:20 +0800 X-Gm-Features: AQROBzDWdqHGg-M4kS1XNQYWUn_uwsptQA0MqyoJaeG-NK2dFINJXSJUrAdxWUY Message-ID: Subject: [PATCH v2 1/2] Check if linker supports -z separate-code To: GNU C Library , WANG Rui X-Spam-Status: No, score=-3010.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~patchwork=sourceware.org@sourceware.org On Fri, Apr 17, 2026 at 12:09 PM H.J. Lu wrote: > > Set have-separate-code to yes if linker supports -z separate-code. > Unchanged from v1. From c9b366a4b5afa30e0f4dd5022ab74cbc47207ae7 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Tue, 14 Apr 2026 11:06:31 +0800 Subject: [PATCH v2] x86: Zero ZMM16-31 when zeroing all call used registers When zeroing all call used registers with AVX512F enabled, zero ZMM16-31 explicitly since vzeroall doesn't touch ZMM16-31. Also add a test for zeroing all call used registers with both AVX512F and APX enabled. gcc/ PR target/124876 * config/i386/i386.cc (ix86_zero_call_used_regs): Zero ZMM16-31 if needed. gcc/testsuite/ PR target/124876 * gcc.target/i386/zero-scratch-regs-23.c: Scan vpxord on ZMM16-31. * gcc.target/i386/zero-scratch-regs-33.c: New test. Signed-off-by: H.J. Lu --- gcc/config/i386/i386.cc | 11 ++++ .../gcc.target/i386/zero-scratch-regs-23.c | 16 +++++ .../gcc.target/i386/zero-scratch-regs-33.c | 60 +++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/zero-scratch-regs-33.c diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index dd017bc7ac3..c93ea383668 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -4078,6 +4078,17 @@ ix86_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) { emit_insn (zero_all_vec_insn); all_sse_zeroed = true; + if (TARGET_64BIT && TARGET_AVX512F) + { + rtx zero = CONST0_RTX (V4SFmode); + for (unsigned int regno = XMM16_REG; + regno <= XMM31_REG; + regno++) + { + rtx reg = gen_rtx_REG (V4SFmode, regno); + emit_move_insn (reg, zero); + } + } } /* mm/st registers are shared registers set, we should follow the following diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c index a3285bed8a0..397893faa6c 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c @@ -7,6 +7,22 @@ foo (void) } /* { dg-final { scan-assembler "vzeroall" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm16, %zmm16, %zmm16" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm17, %zmm17, %zmm17" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm18, %zmm18, %zmm18" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm19, %zmm19, %zmm19" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm20, %zmm20, %zmm20" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm21, %zmm21, %zmm21" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm22, %zmm22, %zmm22" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm23, %zmm23, %zmm23" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm24, %zmm24, %zmm24" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm25, %zmm25, %zmm25" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm26, %zmm26, %zmm26" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm27, %zmm27, %zmm27" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm28, %zmm28, %zmm28" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm29, %zmm29, %zmm29" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm30, %zmm30, %zmm30" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm31, %zmm31, %zmm31" { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "fldz" 8 } } */ /* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-33.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-33.c new file mode 100644 index 00000000000..f40fe2a5377 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-33.c @@ -0,0 +1,60 @@ +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */ +/* { dg-options "-O2 -fzero-call-used-regs=all -march=corei7 -mavx512f -mapxf" } */ + +void +foo (void) +{ +} + +/* { dg-final { scan-assembler "vzeroall" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm16, %zmm16, %zmm16" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm17, %zmm17, %zmm17" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm18, %zmm18, %zmm18" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm19, %zmm19, %zmm19" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm20, %zmm20, %zmm20" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm21, %zmm21, %zmm21" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm22, %zmm22, %zmm22" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm23, %zmm23, %zmm23" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm24, %zmm24, %zmm24" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm25, %zmm25, %zmm25" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm26, %zmm26, %zmm26" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm27, %zmm27, %zmm27" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm28, %zmm28, %zmm28" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm29, %zmm29, %zmm29" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm30, %zmm30, %zmm30" } } */ +/* { dg-final { scan-assembler "vpxord\[ \t\]+%zmm31, %zmm31, %zmm31" } } */ +/* { dg-final { scan-assembler-times "fldz" 8 } } */ +/* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%ecx, %ecx" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%esi, %esi" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r8d, %r8d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r9d, %r9d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r10d, %r10d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r11d, %r11d" } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k0, %k0, %k0" } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k1, %k1, %k1" } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k2, %k2, %k2" } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k3, %k3, %k3" } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k4, %k4, %k4" } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k5, %k5, %k5" } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k6, %k6, %k6" } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k7, %k7, %k7" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r16d, %r16d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r17d, %r17d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r18d, %r18d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r19d, %r19d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r20d, %r20d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r21d, %r21d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r22d, %r22d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r23d, %r23d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r24d, %r24d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r25d, %r25d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r26d, %r26d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r27d, %r27d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r28d, %r28d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r29d, %r29d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r30d, %r30d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%r31d, %r31d" } } */ -- 2.53.0