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([2804:1b3:a7c3:b4d:40f6:149e:b5cc:dca4]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11b06088625sm456271c88.8.2025.11.13.10.50.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Nov 2025 10:50:21 -0800 (PST) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Florian Weimer , Stefan Liebler , Wilco Dijkstra Subject: [PATCH v2] Revert __HAVE_64B_ATOMICS configure check Date: Thu, 13 Nov 2025 15:49:56 -0300 Message-ID: <20251113185018.3744-1-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, PROLO_LEO2, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~patchwork=sourceware.org@sourceware.org The 53807741fb44edb8e7c094cb5e7d4ff4e92a6ec1 added a configure check for 64-bit atomic operations that were not previously enabled on some 32-bit ABIs. However, the NPTL semaphore code casts a sem_t to a new_sem and issues a 64-bit atomic operation for __HAVE_64B_ATOMICS. Since sem_t has 32-bit alignment on 32-bit architectures, this prevents the use of 64-bit atomics even if the ABI supports them. Assume 64-bit atomic support from __WORDSIZE, which maps to how glibc defines it before the broken change (m68k still explicitly sets __HAVE_64B_ATOMICS to 1, but since it does not have multicore support, it should not matter). Checked on x86_64-linux-gnu and i686-linux-gnu. --- config.h.in | 3 --- configure | 42 -------------------------------- configure.ac | 27 -------------------- include/atomic.h | 5 ---- sysdeps/alpha/atomic-machine.h | 7 +++++- sysdeps/generic/atomic-machine.h | 12 +++++++++ sysdeps/riscv/atomic-machine.h | 2 ++ sysdeps/sparc/atomic-machine.h | 6 +++-- sysdeps/x86/atomic-machine.h | 2 ++ 9 files changed, 26 insertions(+), 80 deletions(-) diff --git a/config.h.in b/config.h.in index 4204dbf1236..a7cc17df8ed 100644 --- a/config.h.in +++ b/config.h.in @@ -222,9 +222,6 @@ /* An integer used to scale the timeout of test programs. */ #define TIMEOUTFACTOR 1 -/* Set to 1 if 64 bit atomics are supported. */ -#undef __HAVE_64B_ATOMICS 0 - /* */ diff --git a/configure b/configure index df51b0c1a37..d1e956cc3d3 100755 --- a/configure +++ b/configure @@ -7702,48 +7702,6 @@ if test "$libc_cv_gcc_builtin_memset" = yes ; then fi -{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for 64-bit atomic support" >&5 -printf %s "checking for 64-bit atomic support... " >&6; } -if test ${libc_cv_gcc_has_64b_atomics+y} -then : - printf %s "(cached) " >&6 -else case e in #( - e) cat > conftest.c <<\EOF -typedef struct { long long t; } X; -extern void has_64b_atomics(void); -void f(void) -{ - X x; - /* Use address of structure with 64-bit type. This avoids incorrect - implementations which return true even if long long is not 64-bit aligned. - This works on GCC and LLVM - other cases have bugs and they disagree. */ - _Static_assert (__atomic_always_lock_free (sizeof (x), &x), "no_64b_atomics"); -} -EOF -if { ac_try='${CC-cc} -O2 -S conftest.c' - { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 - (eval $ac_try) 2>&5 - ac_status=$? - printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; }; }; -then - libc_cv_gcc_has_64b_atomics=yes -else - libc_cv_gcc_has_64b_atomics=no -fi -rm -f conftest* ;; -esac -fi -{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $libc_cv_gcc_has_64b_atomics" >&5 -printf "%s\n" "$libc_cv_gcc_has_64b_atomics" >&6; } -if test "$libc_cv_gcc_has_64b_atomics" = yes; then - printf "%s\n" "#define __HAVE_64B_ATOMICS 1" >>confdefs.h - -else - printf "%s\n" "#define __HAVE_64B_ATOMICS 0" >>confdefs.h - - fi - { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for redirection of built-in functions" >&5 printf %s "checking for redirection of built-in functions... " >&6; } if test ${libc_cv_gcc_builtin_redirection+y} diff --git a/configure.ac b/configure.ac index dd0b7a4c7c4..35f69f99c1e 100644 --- a/configure.ac +++ b/configure.ac @@ -1493,33 +1493,6 @@ if test "$libc_cv_gcc_builtin_memset" = yes ; then AC_DEFINE(HAVE_BUILTIN_MEMSET) fi -AC_CACHE_CHECK(for 64-bit atomic support, libc_cv_gcc_has_64b_atomics, [dnl -cat > conftest.c <<\EOF -typedef struct { long long t; } X; -extern void has_64b_atomics(void); -void f(void) -{ - X x; - /* Use address of structure with 64-bit type. This avoids incorrect - implementations which return true even if long long is not 64-bit aligned. - This works on GCC and LLVM - other cases have bugs and they disagree. */ - _Static_assert (__atomic_always_lock_free (sizeof (x), &x), "no_64b_atomics"); -} -EOF -dnl -if AC_TRY_COMMAND([${CC-cc} -O2 -S conftest.c]); -then - libc_cv_gcc_has_64b_atomics=yes -else - libc_cv_gcc_has_64b_atomics=no -fi -rm -f conftest* ]) -if test "$libc_cv_gcc_has_64b_atomics" = yes; then - AC_DEFINE(__HAVE_64B_ATOMICS, 1) -else - AC_DEFINE(__HAVE_64B_ATOMICS, 0) - fi - AC_CACHE_CHECK(for redirection of built-in functions, libc_cv_gcc_builtin_redirection, [dnl cat > conftest.c <<\EOF extern char *strstr (const char *, const char *) __asm ("my_strstr"); diff --git a/include/atomic.h b/include/atomic.h index bac7423ec54..7c0eac365ed 100644 --- a/include/atomic.h +++ b/include/atomic.h @@ -117,11 +117,6 @@ #endif -/* This is equal to 1 iff the architecture supports 64b atomic operations. */ -#ifndef __HAVE_64B_ATOMICS -#error Unable to determine if 64-bit atomics are present. -#endif - /* The following functions are a subset of the atomic operations provided by C11. Usually, a function named atomic_OP_MO(args) is equivalent to C11's atomic_OP_explicit(args, memory_order_MO); exceptions noted below. */ diff --git a/sysdeps/alpha/atomic-machine.h b/sysdeps/alpha/atomic-machine.h index 9aec2317488..b7ce8c4726d 100644 --- a/sysdeps/alpha/atomic-machine.h +++ b/sysdeps/alpha/atomic-machine.h @@ -15,6 +15,11 @@ License along with the GNU C Library. If not, see . */ -#include +#ifndef _ALPHA_ATOMIC_MACHINE_H +#define _ALPHA_ATOMIC_MACHINE_H + +#include_next #define atomic_write_barrier() __asm ("wmb" : : : "memory"); + +#endif diff --git a/sysdeps/generic/atomic-machine.h b/sysdeps/generic/atomic-machine.h index 9f8528c1f2a..0b183919e49 100644 --- a/sysdeps/generic/atomic-machine.h +++ b/sysdeps/generic/atomic-machine.h @@ -34,4 +34,16 @@ and adaptive mutexes to optimize spin-wait loops. */ +#include + +/* NB: The NPTL semaphore code casts a sem_t to a new_sem and issues a 64-bit + atomic operation for __HAVE_64B_ATOMICS. However, the sem_t has 32-bit + alignment on 32-bit architectures, which prevents using 64-bit atomics even + if the ABI supports it. */ +#if __WORDSIZE == 64 +# define __HAVE_64B_ATOMICS 1 +#else +# define __HAVE_64B_ATOMICS 0 +#endif + #endif /* atomic-machine.h */ diff --git a/sysdeps/riscv/atomic-machine.h b/sysdeps/riscv/atomic-machine.h index b6494b3c837..e375c6665e9 100644 --- a/sysdeps/riscv/atomic-machine.h +++ b/sysdeps/riscv/atomic-machine.h @@ -21,6 +21,8 @@ #ifdef __riscv_atomic +#include_next + /* Miscellaneous. */ # define asm_amo(which, ordering, mem, value) ({ \ diff --git a/sysdeps/sparc/atomic-machine.h b/sysdeps/sparc/atomic-machine.h index b8c1e96eb46..2ffcbb2fcf3 100644 --- a/sysdeps/sparc/atomic-machine.h +++ b/sysdeps/sparc/atomic-machine.h @@ -16,8 +16,10 @@ License along with the GNU C Library; if not, see . */ -#ifndef _ATOMIC_MACHINE_H -#define _ATOMIC_MACHINE_H 1 +#ifndef _SPARC_ATOMIC_MACHINE_H +#define _SPARC_ATOMIC_MACHINE_H 1 + +#include_next #ifdef __sparc_v9__ # define atomic_full_barrier() \ diff --git a/sysdeps/x86/atomic-machine.h b/sysdeps/x86/atomic-machine.h index 0681f579879..c854f40dea2 100644 --- a/sysdeps/x86/atomic-machine.h +++ b/sysdeps/x86/atomic-machine.h @@ -19,6 +19,8 @@ #ifndef _X86_ATOMIC_MACHINE_H #define _X86_ATOMIC_MACHINE_H 1 +#include_next + #define atomic_spin_nop() __asm ("pause") #endif /* atomic-machine.h */