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Wed, 18 Jun 2025 14:33:38 +0000 From: Jovan Dmitrovic To: "libc-alpha@sourceware.org" CC: Djordje Todorovic , Joseph Myers , Adhemerval Zanella Netto , DJ Delorie , Jovan Dmitrovic Subject: [PATCH v2 1/8] stdio: Add more setvbuf tests Thread-Topic: [PATCH v2 1/8] stdio: Add more setvbuf tests Thread-Index: AQHb4F36ss43Ua7dMUKawLBWoKxfqA== Date: Wed, 18 Jun 2025 14:33:38 +0000 Message-ID: <20250618143327.2665823-2-jovan.dmitrovic@htecgroup.com> References: <20250618143327.2665823-1-jovan.dmitrovic@htecgroup.com> In-Reply-To: <20250618143327.2665823-1-jovan.dmitrovic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PAVPR09MB6451:EE_|PAWPR09MB6834:EE_ x-ms-office365-filtering-correlation-id: c46bbf76-afd0-4f53-75f9-08ddae751d4e x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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\ $(evaluate-test) +CFLAGS-tst-setvbuf2.c += -DIND_PROC=\"$(objpfx)tst-setvbuf2-ind\" +$(objpfx)tst-setvbuf2-ind : $(objpfx)tst-setvbuf2-ind.o +$(objpfx)tst-setvbuf2.out: $(objpfx)tst-setvbuf2-ind + $(objpfx)tst-printf-round: $(libm) $(objpfx)tst-scanf-round: $(libm) diff --git a/stdio-common/tst-setvbuf2-ind.c b/stdio-common/tst-setvbuf2-ind.c new file mode 100644 index 0000000000..fda2942c24 --- /dev/null +++ b/stdio-common/tst-setvbuf2-ind.c @@ -0,0 +1,2 @@ +#define INDEPENDENT_PART 1 +#include "tst-setvbuf2.c" diff --git a/stdio-common/tst-setvbuf2.c b/stdio-common/tst-setvbuf2.c new file mode 100644 index 0000000000..6cc83355f3 --- /dev/null +++ b/stdio-common/tst-setvbuf2.c @@ -0,0 +1,1030 @@ +/* Test setvbuf under various conditions. + Copyright (C) 2025 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +/* This file is used twice, once as the test itself (where do_test + is defined) and once as a subprocess we spawn to test stdin et all + (where main is defined). INDEPENDENT_PART is defined for the + latter. + + Note also that the purpose of this test is to test setvbuf, not the + underlying buffering code. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Dear future developer: If you are reading this, you are likely + trying to change or understand this test. In that case, these + debug/dump macros will be helpful. */ +#if 0 +# define debug printf ("\033[3%dm%s:%d\033[0m\n", \ + (__LINE__ % 6) + 1, __FUNCTION__, __LINE__); + +static void +dumpfp (FILE *fp) +{ + char f[10], *p=f; + + if (fp->_flags & _IO_UNBUFFERED) + *p++ = 'N'; + if (fp->_flags & _IO_LINE_BUF) + *p++ = 'L'; + if (p == f) + *p++ = 'B'; + *p = 0; + + printf ("FILE %p flags %s" + " read %p \033[%dm%+ld \033[%dm%+ld\033[0m" + " write %p \033[%dm%+ld \033[%dm%+ld\033[0m %ld" + " buf %p \033[%dm%+ld\033[0m sz %ld pend %ld\n", + fp, f, + + fp->_IO_read_base, + fp->_IO_read_ptr == fp->_IO_read_base ? 33 : 32, + fp->_IO_read_ptr - fp->_IO_read_base, + fp->_IO_read_end == fp->_IO_read_base ? 33 : 36, + fp->_IO_read_end - fp->_IO_read_base, + + fp->_IO_write_base, + fp->_IO_write_ptr == fp->_IO_write_base ? 33 : 32, + fp->_IO_write_ptr - fp->_IO_write_base, + fp->_IO_write_end == fp->_IO_write_base ? 33 : 36, + fp->_IO_write_end - fp->_IO_write_base, + fp->_IO_write_end - fp->_IO_write_base, + + fp->_IO_buf_base, + fp->_IO_buf_end == fp->_IO_buf_base ? 33 : 35, + fp->_IO_buf_end - fp->_IO_buf_base, + __fbufsize (fp), __fpending (fp) + ); +} +#else +# define debug +# define dumpfp(FP) +#endif + +#ifndef INDEPENDENT_PART +/* st_blksize value for that file, or BUFSIZ if out of range. */ +static int blksize = BUFSIZ; +#endif + +/* Our test buffer. */ +#define TEST_BUFSIZE 42 +static int bufsize = TEST_BUFSIZE < BUFSIZ ? TEST_BUFSIZE : BUFSIZ; +static char *buffer; + +/* Test data, both written to that file and used as an in-memory + stream. */ +char test_data[2 * BUFSIZ]; + +#define TEST_STRING "abcdef\n" + +enum test_source_case + { + test_source_file, + test_source_pipe, + test_source_fifo, + test_source_pseudo_terminal, + test_source_dev_null, + test_source_count, + }; + +static const char *const test_source_name[test_source_count] = + { + "regular file", + "pipe", + "fifo", + "pseudo_terminal", + "dev_null" + }; + +enum test_stream_case + { + test_stream_stdin, + test_stream_stdout, + test_stream_stderr, + test_stream_fopen_r, + test_stream_fdopen_r, + test_stream_fopen_w, + test_stream_fdopen_w, + test_stream_count + }; + +static bool test_stream_reads[test_stream_count] = + { + true, + false, + false, + true, + true, + false, + false + }; + +static const char *const test_stream_name[test_stream_count] = + { + "stdin", + "stdout", + "stderr", + "fopen (read)", + "fdopen (read)", + "fopen (write)", + "fdopen (write)" + }; + +enum test_config_case + { + test_config_none, + test_config_unbuffered, + test_config_line, + test_config_fully, + test_config_count + }; + +static const char *const test_config_name[test_config_count] = + { + "no change", + "unbuffered", + "line buffered", + "fully buffered" + }; + +FILE *test_stream; + +char *test_file_name = NULL; +int pty_fd; +char *test_pipe_name = NULL; +int test_pipe[2]; + +/* This is either -1 or represents a pre-opened file descriptor for + the test as returned by prepare_test_file. */ +int test_fd; + +/*------------------------------------------------------------*/ + +/* Note that throughout this test we reopen, remove, and change + to/from a fifo, the test file. This would normally cause a race + condition, except that we're in a test container. No other process + can run in the test container simultaneously. */ + +void +prepare_test_data (void) +{ + buffer = (char *) xmalloc (bufsize); + +#ifndef INDEPENDENT_PART + /* Both file and pipe need this. */ + if (test_file_name == NULL) + { + debug; + int fd = create_temp_file ("tst-setvbuf2", &test_file_name); + TEST_VERIFY_EXIT (fd != -1); + struct stat64 st; + xfstat64 (fd, &st); + if (st.st_blksize > 0 && st.st_blksize < BUFSIZ) + blksize = st.st_blksize; + xclose (fd); + } +#endif + + for (size_t i = 0; i < 2 * BUFSIZ; i++) + { + unsigned char c = TEST_STRING[i % strlen (TEST_STRING)]; + test_data[i] = c; + } +} + +#ifndef INDEPENDENT_PART + +/* These functions provide a source/sink for the "other" side of any + pipe-style descriptor we're using for test. */ + +static pthread_t writer_thread_tid = 0; +static pthread_t reader_thread_tid = 0; + +typedef struct { + int fd; + const char *fname; +} ThreadData; +/* It's OK if this is static, we only run one at a time. */ +ThreadData thread_data; + +static void * +writer_thread_proc (void *closure) +{ + ThreadData *td = (ThreadData *) closure; + int fd; + int i; + ssize_t wn; + debug; + + if (td->fname) + td->fd = xopen (td->fname, O_WRONLY, 0777); + fd = td->fd; + + while (1) + { + i = 0; + while (i < BUFSIZ) + { + wn = write (fd, test_data + i, BUFSIZ - i); + if (wn <= 0) + break; + i += wn; + } + } + return NULL; +} + +static void * +reader_thread_proc (void *closure) +{ + ThreadData *td = (ThreadData *) closure; + int fd; + ssize_t rn; + int n = 0; + debug; + + if (td->fname) + td->fd = xopen (td->fname, O_RDONLY, 0777); + fd = td->fd; + + while (1) + { + char buf[BUFSIZ]; + rn = read (fd, buf, BUFSIZ); + if (rn <= 0) + break; + TEST_COMPARE_BLOB (buf, rn, test_data+n, rn); + n += rn; + } + return NULL; +} + +static void +start_writer_thread (int fd) +{ + debug; + thread_data.fd = fd; + thread_data.fname = NULL; + writer_thread_tid = xpthread_create (NULL, writer_thread_proc, + (void *)&thread_data); +} + +static void +start_writer_thread_n (const char *fname) +{ + debug; + thread_data.fd = 0; + thread_data.fname = fname; + writer_thread_tid = xpthread_create (NULL, writer_thread_proc, + (void *)&thread_data); +} + +static void +end_writer_thread (void) +{ + debug; + if (writer_thread_tid) + { + pthread_cancel (writer_thread_tid); + xpthread_join (writer_thread_tid); + xclose (thread_data.fd); + writer_thread_tid = 0; + } +} + +static void +start_reader_thread (int fd) +{ + debug; + thread_data.fd = fd; + thread_data.fname = NULL; + reader_thread_tid = xpthread_create (NULL, reader_thread_proc, + (void *)&thread_data); +} + +static void +start_reader_thread_n (const char *fname) +{ + debug; + thread_data.fd = 0; + thread_data.fname = fname; + reader_thread_tid = xpthread_create (NULL, reader_thread_proc, + (void *)&thread_data); +} + +static void +end_reader_thread (void) +{ + debug; + if (reader_thread_tid) + { + pthread_cancel (reader_thread_tid); + xpthread_join (reader_thread_tid); + xclose (thread_data.fd); + reader_thread_tid = 0; + } +} + +/*------------------------------------------------------------*/ + +/* These two functions are reponsible for choosing a file to be tested + against, typically by returning a filename but in a few cases also + providing a file descriptor (i.e. for fdopen). */ + +static const char * +prepare_test_file (enum test_source_case f, enum test_stream_case s) +{ + debug; + + test_fd = -1; + + switch (f) + { + case test_source_file: + { + if (test_stream_reads[f]) + { + debug; + FILE *fp = xfopen (test_file_name, "w"); + TEST_VERIFY_EXIT (fwrite (test_data, 1, 2 * BUFSIZ, fp) + == 2 * BUFSIZ); + xfclose (fp); + } + debug; + return test_file_name; + } + + case test_source_pipe: + { + debug; + xpipe (test_pipe); + if (test_stream_reads[s]) + { + start_writer_thread (test_pipe[1]); + test_fd = test_pipe[0]; + } + else + { + start_reader_thread (test_pipe[0]); + test_fd = test_pipe[1]; + } + test_pipe_name = xasprintf ("/proc/self/fd/%d", test_fd); + debug; + return test_pipe_name; + } + + case test_source_fifo: + { + /* We do not want to fail/exit if the file doesn't exist. */ + unlink (test_file_name); + xmkfifo (test_file_name, 0600); + debug; + if (test_stream_reads[s]) + start_writer_thread_n (test_file_name); + else + start_reader_thread_n (test_file_name); + debug; + return test_file_name; + } + + case test_source_pseudo_terminal: + { + support_openpty (&pty_fd, &test_fd, &test_pipe_name, NULL, NULL); + + debug; + if (test_stream_reads[s]) + start_writer_thread (pty_fd); + else + start_reader_thread (pty_fd); + + debug; + return test_pipe_name; + } + + case test_source_dev_null: + debug; + return "/dev/null"; + + default: + abort (); + } +} + +static void +unprepare_test_file (FILE *fp, + enum test_source_case f, + enum test_stream_case s) +{ + debug; + switch (f) + { + case test_source_file: + break; + + case test_source_pipe: + free (test_pipe_name); + if (test_stream_reads[s]) + end_writer_thread (); + else + end_reader_thread (); + break; + + case test_source_fifo: + if (test_stream_reads[s]) + end_writer_thread (); + else + end_reader_thread (); + unlink (test_file_name); + break; + + case test_source_pseudo_terminal: + free (test_pipe_name); + if (test_stream_reads[s]) + end_writer_thread (); + else + end_reader_thread (); + break; + + case test_source_dev_null: + break; + + default: + abort (); + } + debug; +} + +/*------------------------------------------------------------*/ + +/* This function takes a filename and returns a file descriptor, + opened according to the method requested. */ + +static FILE * +open_test_stream (enum test_source_case f, enum test_stream_case s) +{ + int fd; + FILE *fp; + const char *fname; + + debug; + fname = prepare_test_file (f, s); + if (fname == NULL) + return NULL; + + switch (s) + { + case test_stream_stdin: + fp = xfopen (fname, "r"); + break; + + case test_stream_stdout: + fp = xfopen (fname, "w"); + break; + + case test_stream_stderr: + fp = xfopen (fname, "w"); + break; + + case test_stream_fopen_r: + fp = xfopen (fname, "r"); + break; + + case test_stream_fdopen_r: + if (test_fd == -1) + fd = xopen (fname, O_RDONLY, 0); + else + fd = test_fd; + fp = fdopen (fd, "r"); + break; + + case test_stream_fopen_w: + fp = xfopen (fname, "w"); + break; + + case test_stream_fdopen_w: + fd = xopen (fname, O_WRONLY|O_CREAT|O_TRUNC, 0777); + fp = fdopen (fd, "w"); + break; + + default: + abort (); + } + TEST_VERIFY_EXIT (fp != NULL); + + if (f == test_source_pseudo_terminal) + { + struct termios t; + /* We disable the NL to CR-LF conversion so that we can compare + data without having to remove the extra CRs. */ + if (tcgetattr (fileno (fp), &t) < 0) + FAIL_EXIT1 ("tcgetattr failed: %m"); + t.c_oflag &= ~ONLCR; + if (tcsetattr (fileno (fp), TCSANOW, &t) < 0) + FAIL_EXIT1 ("tcsetattr failed: %m"); + } + + debug; + printf ("source %s stream %s file %s fd %d\n", + test_source_name[f], + test_stream_name[s], fname, fileno (fp)); + return fp; +} + +#endif + +/*------------------------------------------------------------*/ + +/* These functions do the actual testing - setting various buffering + options and verifying that they buffer as expected. */ + +static void +test_put_string (FILE *fp, const char *s, int count) +{ + while (*s && count--) + { + fputc (*s++, fp); + TEST_VERIFY_EXIT (!ferror (fp)); + } +} + +int +verify_fully_buffered (FILE *fp, + enum test_source_case f, + enum test_stream_case s, + enum test_config_case c) +{ + debug; + if (test_stream_reads[s]) + { + char buf[10]; + dumpfp (fp); + size_t fc = fread (buf, 1, 10 - 1, fp); + dumpfp (fp); + + ssize_t count = fp->_IO_read_ptr - fp->_IO_read_base; + + TEST_VERIFY (fp->_IO_read_base != NULL); + if (f == test_source_dev_null) + { + TEST_VERIFY (fc == 0); + TEST_VERIFY (count == 0); + } + else if (f == test_source_pseudo_terminal) + { + TEST_VERIFY (fc == 9); + TEST_VERIFY (count == 3 || count == 10); + } + else + { + TEST_VERIFY (fc == 9); + TEST_VERIFY (count == 10); + } + + /* We already checked for the first character being 'a'. */ + if (count > 1) + { + TEST_COMPARE_BLOB (buf, count - 1, test_data + 1, count - 1); + TEST_COMPARE_BLOB (fp->_IO_read_base, count, test_data, count); + } + } + else + { + dumpfp (fp); + test_put_string (fp, test_data + 1, 10 - 1); + dumpfp (fp); + TEST_COMPARE (fp->_IO_write_ptr - fp->_IO_write_base, 10); + TEST_COMPARE_BLOB (fp->_IO_write_base, 10, test_data, 10); + } + + TEST_COMPARE ((fp->_flags & (_IO_UNBUFFERED | _IO_LINE_BUF)), 0); + if (c != test_config_none) + TEST_COMPARE (__fbufsize (fp), bufsize); + return 0; +} + +int +verify_line_buffered (FILE *fp, + enum test_source_case f, + enum test_stream_case s, + enum test_config_case c) +{ + debug; + /* "line buffered" for inputs is not really defined; what you really + want here is to control the device providing input. For GLIBC a + line-buffered input is treated as fully buffered. */ + if (test_stream_reads[s]) + { + char buf[10]; + dumpfp (fp); + size_t fc = fread (buf, 1, 10 - 1, fp); + dumpfp (fp); + + ssize_t count = fp->_IO_read_ptr - fp->_IO_read_base; + + TEST_VERIFY (fp->_IO_read_base != NULL); + if (f == test_source_dev_null) + { + TEST_VERIFY (fc == 0); + TEST_VERIFY (count == 0); + } + else if (f == test_source_pseudo_terminal) + { + TEST_VERIFY (fc == 9); + TEST_VERIFY (count == 3 || count == 10); + } + else + { + TEST_VERIFY (fc == 9); + TEST_VERIFY (count == 10); + } + + /* We already checked for the first character being 'a'. */ + if (count > 1) + { + TEST_COMPARE_BLOB (buf, count - 1, test_data + 1, count - 1); + TEST_COMPARE_BLOB (fp->_IO_read_base, count, test_data, count); + } + } + else + { + dumpfp (fp); + test_put_string (fp, test_data + 1, 10 - 1); + dumpfp (fp); + TEST_COMPARE (fp->_IO_write_ptr - fp->_IO_write_base, 3); + /* The first "abcdef\n" got flushed, leaving "abc". */ + TEST_COMPARE_BLOB (fp->_IO_write_base, 3, test_data + 7, 3); + } + + TEST_COMPARE ((fp->_flags & (_IO_UNBUFFERED | _IO_LINE_BUF)), _IO_LINE_BUF); + if (c != test_config_none) + TEST_COMPARE (__fbufsize (fp), bufsize); + return 0; +} + +int +verify_unbuffered (FILE *fp, + enum test_source_case f, + enum test_stream_case s, + enum test_config_case c) +{ + debug; + if (test_stream_reads[s]) + { + /* We've already read one byte. */ + dumpfp (fp); + TEST_VERIFY (fp->_IO_read_base != NULL); + if (f == test_source_dev_null) + TEST_COMPARE (fp->_IO_read_ptr - fp->_IO_read_base, 0); + else + { + TEST_COMPARE (fp->_IO_read_ptr - fp->_IO_read_base, 1); + TEST_COMPARE (fp->_IO_read_base[0], test_data[0]); + TEST_VERIFY (fp->_IO_read_ptr == fp->_IO_read_end); + } + } + else + { + dumpfp (fp); + fputc (test_data[1], fp); + dumpfp (fp); + TEST_COMPARE (fp->_IO_write_ptr - fp->_IO_write_base, 0); + TEST_COMPARE (fp->_IO_write_base[0], test_data[1]); + TEST_VERIFY (fp->_IO_write_end == fp->_IO_write_base); + } + TEST_COMPARE ((fp->_flags & (_IO_UNBUFFERED | _IO_LINE_BUF)), + _IO_UNBUFFERED); + TEST_COMPARE (__fbufsize (fp), 1); + return 0; +} + +static int +do_setvbuf (FILE *fp, void *buf, int flags, int size, + enum test_stream_case s) +{ + if (s != test_stream_stdout) + printf ("SETVBUF %p %p %s %d\n", + fp, buf, + flags == _IONBF ? "_IONBF" + : flags == _IOLBF ? "_IOLBF" + : flags == _IOFBF ? "_IOFBF" + : "???", size); + if (setvbuf (fp, buf, flags, size)) + { + perror ("setvbuf"); + return 1; + } + return 0; +} + +int +do_second_part (FILE *fp, + enum test_source_case f, + enum test_stream_case s, + enum test_config_case c) +{ + /* At this point, FP is the stream to test according to the other + parameters. */ + + int rv = 0; + int flags_before; + int flags_after; + + debug; + + flags_before = fp->_flags & (_IO_UNBUFFERED | _IO_LINE_BUF); + + /* This is where we do the thing we're testing for. */ + switch (c) + { + case test_config_none: + /* Buffering is unchanged. */ + break; + + case test_config_unbuffered: + do_setvbuf (fp, NULL, _IONBF, 0, s); + break; + + case test_config_line: + do_setvbuf (fp, buffer, _IOLBF, bufsize, s); + break; + + case test_config_fully: + do_setvbuf (fp, buffer, _IOFBF, bufsize, s); + break; + + default: + abort (); + } + + flags_after = fp->_flags & (_IO_UNBUFFERED | _IO_LINE_BUF); + + /* Check the buffer mode after we touch it, if we touched it. */ + switch (c) + { + case test_config_none: + /* Buffering is unchanged, but may change on the first read/write. */ + TEST_COMPARE (flags_after, flags_before); + break; + + case test_config_unbuffered: + TEST_COMPARE (flags_after, _IO_UNBUFFERED); + break; + + case test_config_line: + TEST_COMPARE (flags_after, _IO_LINE_BUF); + break; + + case test_config_fully: + TEST_COMPARE (flags_after, 0); + break; + + default: + abort (); + } + + /* Glibc defers calculating the appropriate buffering mechanism + until it reads from or writes to the device. So we read one + character here, and account for that in the tests. */ + if (test_stream_reads[s]) + { + dumpfp (fp); + int c = fgetc (fp); + if (c != TEST_STRING[0] && f != test_source_dev_null) + FAIL ("first char read is %c not %c", c, TEST_STRING[0]); + dumpfp (fp); + } + else + { + dumpfp (fp); + fputc (TEST_STRING[0], fp); + dumpfp (fp); + } + + switch (fp->_flags & (_IO_UNBUFFERED | _IO_LINE_BUF)) + { + case _IO_LINE_BUF: + rv += verify_line_buffered (fp, f, s, c); + break; + + case _IO_UNBUFFERED: + rv += verify_unbuffered (fp, f, s, c); + break; + + case 0: /* Fully buffered. */ + rv += verify_fully_buffered (fp, f, s, c); + break; + + default: + abort (); + } + + + fclose (fp); + return rv; +} + +/*------------------------------------------------------------*/ + +#ifdef INDEPENDENT_PART +/* This part is the independent sub-process we call to test stdin et + al. */ + +int +main (int argc, char **argv) +{ + /* This is one of the subprocesses we created to test stdin et + al. */ + FILE *fp; + + /* If we're called as a regular test, instead of as a sub-process, + don't complain. */ + if (argc == 1) + return 0; + + if (argc != 4) + { + int i; + for (i = 0; i <= argc; i ++) + printf ("argv[%d] = `%s'\n", i, argv[i] ?: "(null)"); + FAIL_EXIT1 ("sub-process called wrong"); + } + + prepare_test_data (); + + enum test_source_case f = atoi (argv[1]); + enum test_stream_case s = atoi (argv[2]); + enum test_config_case c = atoi (argv[3]); + + if (s != test_stream_stdout) + printf ("\n\033[41mRunning test %s : %s : %s\033[0m\n", + test_source_name[f], + test_stream_name[s], + test_config_name[c]); + + switch (s) + { + case test_stream_stdin: + fp = stdin; + break; + case test_stream_stdout: + fp = stdout; + break; + case test_stream_stderr: + fp = stderr; + break; + default: + abort (); + } + + return do_second_part (fp, f, s, c); +} + +#else +/* This part is the standard test process. */ + +/* Spawn an independent sub-process with std* redirected. */ +int +recurse (FILE *fp, + enum test_source_case f, + enum test_stream_case s, + enum test_config_case c) +{ + /* We need to test stdin, stdout, or stderr, which means creating a + subprocess with one of those redirected from FP. */ + debug; + + pid_t pid; + int status; + + pid = fork (); + + switch (pid) + { + case -1: /* error */ + perror ("fork"); + return 1; + break; + + default: /* parent */ + fclose (fp); + xwaitpid (pid, &status, 0); + if (WIFEXITED (status) + && WEXITSTATUS (status) == 0) + return 0; + return 1; + + case 0: /* child */ + switch (s) + { + case test_stream_stdin: + xclose (0); + dup2 (fileno (fp), 0); + break; + case test_stream_stdout: + xclose (1); + dup2 (fileno (fp), 1); + break; + case test_stream_stderr: + xclose (2); + dup2 (fileno (fp), 2); + break; + default: + abort (); + } + fclose (fp); + + /* At this point, we have to run a program... which is tricky to + properly support for remote targets or crosses, because of + glibc versions etc. Hence we run in a test-container. */ + + char fs[10], ss[10], cs[10]; + sprintf (fs, "%d", f); + sprintf (ss, "%d", s); + sprintf (cs, "%d", c); + execl (IND_PROC, IND_PROC, fs, ss, cs, NULL); + if (s == test_stream_stdout) + fprintf (stderr, "execl (%s) failed, ", IND_PROC); + else + printf ("execl (%s) failed, ", IND_PROC); + perror ("The error was"); + exit (1); + break; + } + + return 0; +} + +int +do_test (void) +{ + int rv = 0; + + signal (SIGPIPE, SIG_IGN); + + prepare_test_data (); + + for (enum test_source_case f = 0; f < test_source_count; ++f) + for (enum test_stream_case s = 0; s < test_stream_count; ++s) + for (enum test_config_case c = 0; c < test_config_count; ++c) + { + printf ("\n\033[43mRunning test %s : %s : %s\033[0m\n", + test_source_name[f], + test_stream_name[s], + test_config_name[c]); + + FILE *fp = open_test_stream (f, s); + + if (fp) + { + + if (s <= test_stream_stderr) + rv += recurse (fp, f, s, c); + else + rv += do_second_part (fp, f, s, c); + + unprepare_test_file (fp, f, s); + } + } + + free (buffer); + + printf ("return %d\n", rv); + return rv; +} + +# include +#endif + From patchwork Wed Jun 18 14:33:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jovan Dmitrovic X-Patchwork-Id: 114674 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 317BD38302B0 for ; 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Cherry-picked 94a52199502361be4a5b1cc616661e287416cc8d from https://github.com/MIPS/glibc Signed-off-by: Matthew Fortune Signed-off-by: Andrew Bennett Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic Signed-off-by: Jovan Dmitrović --- sysdeps/mips/add_n.S | 12 +- sysdeps/mips/addmul_1.S | 11 +- sysdeps/mips/dl-machine.h | 15 ++- sysdeps/mips/dl-trampoline.c | 4 - sysdeps/mips/lshift.S | 12 +- sysdeps/mips/machine-gmon.h | 82 +++++++++++++ sysdeps/mips/memcpy.S | 120 +++++++++++-------- sysdeps/mips/memset.S | 62 +++++----- sysdeps/mips/mips32/crtn.S | 12 +- sysdeps/mips/mips64/__longjmp.c | 2 +- sysdeps/mips/mips64/add_n.S | 12 +- sysdeps/mips/mips64/addmul_1.S | 11 +- sysdeps/mips/mips64/lshift.S | 12 +- sysdeps/mips/mips64/mul_1.S | 11 +- sysdeps/mips/mips64/n32/crtn.S | 12 +- sysdeps/mips/mips64/n64/crtn.S | 12 +- sysdeps/mips/mips64/rshift.S | 12 +- sysdeps/mips/mips64/sub_n.S | 12 +- sysdeps/mips/mips64/submul_1.S | 11 +- sysdeps/mips/mul_1.S | 11 +- sysdeps/mips/rshift.S | 12 +- sysdeps/mips/sub_n.S | 12 +- sysdeps/mips/submul_1.S | 11 +- sysdeps/mips/sys/asm.h | 20 +--- sysdeps/unix/mips/mips32/sysdep.h | 4 - sysdeps/unix/mips/mips64/sysdep.h | 4 - sysdeps/unix/mips/sysdep.h | 2 - sysdeps/unix/sysv/linux/mips/mips32/sysdep.h | 10 -- sysdeps/unix/sysv/linux/mips/mips64/sysdep.h | 14 --- 29 files changed, 260 insertions(+), 277 deletions(-) -- 2.34.1 diff --git a/sysdeps/mips/add_n.S b/sysdeps/mips/add_n.S index d9037432f5..8c4ebc1ce2 100644 --- a/sysdeps/mips/add_n.S +++ b/sysdeps/mips/add_n.S @@ -31,19 +31,16 @@ along with the GNU MP Library. If not, see .option pic2 #endif ENTRY (__mpn_add_n) - .set noreorder #ifdef __PIC__ .cpload t9 #endif - .set nomacro - lw $10,0($5) lw $11,0($6) addiu $7,$7,-1 and $9,$7,4-1 /* number of limbs in first loop */ - beq $9,$0,L(L0) /* if multiple of 4 limbs, skip first loop */ move $2,$0 + beq $9,$0,L(L0) /* if multiple of 4 limbs, skip first loop */ subu $7,$7,$9 @@ -61,11 +58,10 @@ L(Loop0): addiu $9,$9,-1 addiu $6,$6,4 move $10,$12 move $11,$13 - bne $9,$0,L(Loop0) addiu $4,$4,4 + bne $9,$0,L(Loop0) L(L0): beq $7,$0,L(end) - nop L(Loop): addiu $7,$7,-4 @@ -108,14 +104,14 @@ L(Loop): addiu $7,$7,-4 addiu $5,$5,16 addiu $6,$6,16 - bne $7,$0,L(Loop) addiu $4,$4,16 + bne $7,$0,L(Loop) L(end): addu $11,$11,$2 sltu $8,$11,$2 addu $11,$10,$11 sltu $2,$11,$10 sw $11,0($4) - j $31 or $2,$2,$8 + jr $31 END (__mpn_add_n) diff --git a/sysdeps/mips/addmul_1.S b/sysdeps/mips/addmul_1.S index d4743b73cf..9ca777e19b 100644 --- a/sysdeps/mips/addmul_1.S +++ b/sysdeps/mips/addmul_1.S @@ -31,12 +31,9 @@ along with the GNU MP Library. If not, see .option pic2 #endif ENTRY (__mpn_addmul_1) - .set noreorder #ifdef __PIC__ .cpload t9 #endif - .set nomacro - /* warm up phase 0 */ lw $8,0($5) @@ -50,12 +47,12 @@ ENTRY (__mpn_addmul_1) #endif addiu $6,$6,-1 - beq $6,$0,L(LC0) move $2,$0 /* zero cy2 */ + beq $6,$0,L(LC0) addiu $6,$6,-1 - beq $6,$0,L(LC1) lw $8,0($5) /* load new s1 limb as early as possible */ + beq $6,$0,L(LC1) L(Loop): lw $10,0($4) #if __mips_isa_rev < 6 @@ -81,8 +78,8 @@ L(Loop): lw $10,0($4) addu $2,$2,$10 sw $3,0($4) addiu $4,$4,4 - bne $6,$0,L(Loop) /* should be "bnel" */ addu $2,$9,$2 /* add high product limb and carry from addition */ + bne $6,$0,L(Loop) /* should be "bnel" */ /* cool down phase 1 */ L(LC1): lw $10,0($4) @@ -123,6 +120,6 @@ L(LC0): lw $10,0($4) sltu $10,$3,$10 addu $2,$2,$10 sw $3,0($4) - j $31 addu $2,$9,$2 /* add high product limb and carry from addition */ + jr $31 END (__mpn_addmul_1) diff --git a/sysdeps/mips/dl-machine.h b/sysdeps/mips/dl-machine.h index 560bf1396c..12d7aaf05d 100644 --- a/sysdeps/mips/dl-machine.h +++ b/sysdeps/mips/dl-machine.h @@ -127,16 +127,13 @@ elf_machine_load_address (void) { ElfW(Addr) addr; #ifndef __mips16 - asm (" .set noreorder\n" - " " STRINGXP (PTR_LA) " %0, 0f\n" + asm (" " STRINGXP (PTR_LA) " %0, 0f\n" # if !defined __mips_isa_rev || __mips_isa_rev < 6 " bltzal $0, 0f\n" - " nop\n" +#else + " bal 0f\n" +#endif "0: " STRINGXP (PTR_SUBU) " %0, $31, %0\n" -# else - "0: addiupc $31, 0\n" - " " STRINGXP (PTR_SUBU) " %0, $31, %0\n" -# endif " .set reorder\n" : "=r" (addr) : /* No inputs */ @@ -237,7 +234,9 @@ do { \ and not just plain _start. */ #ifndef __mips16 -# if !defined __mips_isa_rev || __mips_isa_rev < 6 +/* Although microMIPSr6 has an ADDIUPC instruction, it must be 4-byte aligned + for the address calculation to be valid. */ +# if !defined __mips_isa_rev || __mips_isa_rev < 6 || defined __mips_micromips # define LCOFF STRINGXP(.Lcof2) # define LOAD_31 STRINGXP(bltzal $8) "," STRINGXP(.Lcof2) # else diff --git a/sysdeps/mips/dl-trampoline.c b/sysdeps/mips/dl-trampoline.c index 333c4ba909..4cdd2bc612 100644 --- a/sysdeps/mips/dl-trampoline.c +++ b/sysdeps/mips/dl-trampoline.c @@ -301,7 +301,6 @@ asm ("\n\ .ent _dl_runtime_resolve\n\ _dl_runtime_resolve:\n\ .frame $29, " STRINGXP(ELF_DL_FRAME_SIZE) ", $31\n\ - .set noreorder\n\ # Save GP.\n\ 1: move $3, $28\n\ # Save arguments and sp value in stack.\n\ @@ -311,7 +310,6 @@ _dl_runtime_resolve:\n\ # Compute GP.\n\ 2: " STRINGXP(SETUP_GP) "\n\ " STRINGXV(SETUP_GP64 (0, _dl_runtime_resolve)) "\n\ - .set reorder\n\ # Save slot call pc.\n\ move $2, $31\n\ " IFABIO32(STRINGXP(CPRESTORE(32))) "\n\ @@ -358,7 +356,6 @@ asm ("\n\ .ent _dl_runtime_pltresolve\n\ _dl_runtime_pltresolve:\n\ .frame $29, " STRINGXP(ELF_DL_PLT_FRAME_SIZE) ", $31\n\ - .set noreorder\n\ # Save arguments and sp value in stack.\n\ 1: " STRINGXP(PTR_SUBIU) " $29, " STRINGXP(ELF_DL_PLT_FRAME_SIZE) "\n\ " IFABIO32(STRINGXP(PTR_L) " $13, " STRINGXP(PTRSIZE) "($28)") "\n\ @@ -368,7 +365,6 @@ _dl_runtime_pltresolve:\n\ # Compute GP.\n\ 2: " STRINGXP(SETUP_GP) "\n\ " STRINGXV(SETUP_GP64 (0, _dl_runtime_pltresolve)) "\n\ - .set reorder\n\ " IFABIO32(STRINGXP(CPRESTORE(32))) "\n\ " ELF_DL_PLT_SAVE_ARG_REGS "\ move $4, $13\n\ diff --git a/sysdeps/mips/lshift.S b/sysdeps/mips/lshift.S index d4a4e8e871..b480dc5c6a 100644 --- a/sysdeps/mips/lshift.S +++ b/sysdeps/mips/lshift.S @@ -30,12 +30,9 @@ along with the GNU MP Library. If not, see .option pic2 #endif ENTRY (__mpn_lshift) - .set noreorder #ifdef __PIC__ .cpload t9 #endif - .set nomacro - sll $2,$6,2 addu $5,$5,$2 /* make r5 point at end of src */ lw $10,-4($5) /* load first limb */ @@ -43,8 +40,8 @@ ENTRY (__mpn_lshift) addu $4,$4,$2 /* make r4 point at end of res */ addiu $6,$6,-1 and $9,$6,4-1 /* number of limbs in first loop */ - beq $9,$0,L(L0) /* if multiple of 4 limbs, skip first loop */ srl $2,$10,$13 /* compute function result */ + beq $9,$0,L(L0) /* if multiple of 4 limbs, skip first loop */ subu $6,$6,$9 @@ -56,11 +53,10 @@ L(Loop0): lw $3,-8($5) srl $12,$3,$13 move $10,$3 or $8,$11,$12 - bne $9,$0,L(Loop0) sw $8,0($4) + bne $9,$0,L(Loop0) L(L0): beq $6,$0,L(Lend) - nop L(Loop): lw $3,-8($5) addiu $4,$4,-16 @@ -88,10 +84,10 @@ L(Loop): lw $3,-8($5) addiu $5,$5,-16 or $8,$14,$9 - bgtz $6,L(Loop) sw $8,0($4) + bgtz $6,L(Loop) L(Lend): sll $8,$10,$7 - j $31 sw $8,-4($4) + jr $31 END (__mpn_lshift) diff --git a/sysdeps/mips/machine-gmon.h b/sysdeps/mips/machine-gmon.h index 1f9af72d6b..caae70d224 100644 --- a/sysdeps/mips/machine-gmon.h +++ b/sysdeps/mips/machine-gmon.h @@ -34,6 +34,42 @@ static void __attribute_used__ __mcount (u_long frompc, u_long selfpc) # define CPRESTORE #endif +#if __mips_isa_rev > 5 && defined (__mips_micromips) +#define MCOUNT asm(\ + ".globl _mcount;\n\t" \ + ".align 2;\n\t" \ + ".set push;\n\t" \ + ".set nomips16;\n\t" \ + ".type _mcount,@function;\n\t" \ + ".ent _mcount\n\t" \ + "_mcount:\n\t" \ + ".frame $sp,44,$31\n\t" \ + ".set noat;\n\t" \ + CPLOAD \ + "subu $29,$29,48;\n\t" \ + CPRESTORE \ + "sw $4,24($29);\n\t" \ + "sw $5,28($29);\n\t" \ + "sw $6,32($29);\n\t" \ + "sw $7,36($29);\n\t" \ + "sw $2,40($29);\n\t" \ + "sw $1,16($29);\n\t" \ + "sw $31,20($29);\n\t" \ + "move $5,$31;\n\t" \ + "move $4,$1;\n\t" \ + "balc __mcount;\n\t" \ + "lw $4,24($29);\n\t" \ + "lw $5,28($29);\n\t" \ + "lw $6,32($29);\n\t" \ + "lw $7,36($29);\n\t" \ + "lw $2,40($29);\n\t" \ + "lw $1,20($29);\n\t" \ + "lw $31,16($29);\n\t" \ + "addu $29,$29,56;\n\t" \ + "jrc $1;\n\t" \ + ".end _mcount;\n\t" \ + ".set pop"); +#else #define MCOUNT asm(\ ".globl _mcount;\n\t" \ ".align 2;\n\t" \ @@ -71,6 +107,7 @@ static void __attribute_used__ __mcount (u_long frompc, u_long selfpc) "move $31,$1;\n\t" \ ".end _mcount;\n\t" \ ".set pop"); +#endif #else @@ -97,6 +134,50 @@ static void __attribute_used__ __mcount (u_long frompc, u_long selfpc) # error "Unknown ABI" #endif +#if __mips_isa_rev > 5 && defined (__mips_micromips) +#define MCOUNT asm(\ + ".globl _mcount;\n\t" \ + ".align 3;\n\t" \ + ".set push;\n\t" \ + ".set nomips16;\n\t" \ + ".type _mcount,@function;\n\t" \ + ".ent _mcount\n\t" \ + "_mcount:\n\t" \ + ".frame $sp,88,$31\n\t" \ + ".set noat;\n\t" \ + PTR_SUBU_STRING " $29,$29,96;\n\t" \ + CPSETUP \ + "sd $4,24($29);\n\t" \ + "sd $5,32($29);\n\t" \ + "sd $6,40($29);\n\t" \ + "sd $7,48($29);\n\t" \ + "sd $8,56($29);\n\t" \ + "sd $9,64($29);\n\t" \ + "sd $10,72($29);\n\t" \ + "sd $11,80($29);\n\t" \ + "sd $2,16($29);\n\t" \ + "sd $1,0($29);\n\t" \ + "sd $31,8($29);\n\t" \ + "move $5,$31;\n\t" \ + "move $4,$1;\n\t" \ + "balc __mcount;\n\t" \ + "ld $4,24($29);\n\t" \ + "ld $5,32($29);\n\t" \ + "ld $6,40($29);\n\t" \ + "ld $7,48($29);\n\t" \ + "ld $8,56($29);\n\t" \ + "ld $9,64($29);\n\t" \ + "ld $10,72($29);\n\t" \ + "ld $11,80($29);\n\t" \ + "ld $2,16($29);\n\t" \ + "ld $1,8($29);\n\t" \ + "ld $31,0($29);\n\t" \ + CPRETURN \ + PTR_ADDU_STRING " $29,$29,96;\n\t" \ + "jrc $1;\n\t" \ + ".end _mcount;\n\t" \ + ".set pop"); +#else #define MCOUNT asm(\ ".globl _mcount;\n\t" \ ".align 3;\n\t" \ @@ -142,5 +223,6 @@ static void __attribute_used__ __mcount (u_long frompc, u_long selfpc) "move $31,$1;\n\t" \ ".end _mcount;\n\t" \ ".set pop"); +#endif #endif diff --git a/sysdeps/mips/memcpy.S b/sysdeps/mips/memcpy.S index 1b376b6d9c..8736cfbec6 100644 --- a/sysdeps/mips/memcpy.S +++ b/sysdeps/mips/memcpy.S @@ -86,6 +86,12 @@ # endif #endif +#if __mips_isa_rev > 5 && defined (__mips_micromips) +# define PTR_BC bc16 +#else +# define PTR_BC bc +#endif + /* * Using PREFETCH_HINT_LOAD_STREAMED instead of PREFETCH_LOAD on load * prefetches appear to offer a slight performance advantage. @@ -272,7 +278,6 @@ LEAF(MEMCPY_NAME, 0) LEAF(MEMCPY_NAME) #endif .set nomips16 - .set noreorder /* * Below we handle the case where memcpy is called with overlapping src and dst. * Although memcpy is not required to handle this case, some parts of Android @@ -284,10 +289,9 @@ LEAF(MEMCPY_NAME) xor t1,t0,t2 PTR_SUBU t0,t1,t2 sltu t2,t0,a2 - beq t2,zero,L(memcpy) la t9,memmove + beq t2,zero,L(memcpy) jr t9 - nop L(memcpy): #endif /* @@ -295,12 +299,12 @@ L(memcpy): * size, copy dst pointer to v0 for the return value. */ slti t2,a2,(2 * NSIZE) - bne t2,zero,L(lasts) #if defined(RETURN_FIRST_PREFETCH) || defined(RETURN_LAST_PREFETCH) move v0,zero #else move v0,a0 #endif + bne t2,zero,L(lasts) #ifndef R6_CODE @@ -312,12 +316,12 @@ L(memcpy): */ xor t8,a1,a0 andi t8,t8,(NSIZE-1) /* t8 is a0/a1 word-displacement */ - bne t8,zero,L(unaligned) PTR_SUBU a3, zero, a0 + bne t8,zero,L(unaligned) andi a3,a3,(NSIZE-1) /* copy a3 bytes to align a0/a1 */ + PTR_SUBU a2,a2,a3 /* a2 is the remining bytes count */ beq a3,zero,L(aligned) /* if a3=0, it is already aligned */ - PTR_SUBU a2,a2,a3 /* a2 is the remaining bytes count */ C_LDHI t8,0(a1) PTR_ADDU a1,a1,a3 @@ -332,18 +336,24 @@ L(memcpy): * align instruction. */ andi t8,a0,7 +#ifdef __mips_micromips + auipc t9,%pcrel_hi(L(atable)) + addiu t9,t9,%pcrel_lo(L(atable)+4) + PTR_LSA t9,t8,t9,1 +#else lapc t9,L(atable) PTR_LSA t9,t8,t9,2 +#endif jrc t9 L(atable): - bc L(lb0) - bc L(lb7) - bc L(lb6) - bc L(lb5) - bc L(lb4) - bc L(lb3) - bc L(lb2) - bc L(lb1) + PTR_BC L(lb0) + PTR_BC L(lb7) + PTR_BC L(lb6) + PTR_BC L(lb5) + PTR_BC L(lb4) + PTR_BC L(lb3) + PTR_BC L(lb2) + PTR_BC L(lb1) L(lb7): lb a3, 6(a1) sb a3, 6(a0) @@ -374,20 +384,26 @@ L(lb1): L(lb0): andi t8,a1,(NSIZE-1) +#ifdef __mips_micromips + auipc t9,%pcrel_hi(L(jtable)) + addiu t9,t9,%pcrel_lo(L(jtable)+4) + PTR_LSA t9,t8,t9,1 +#else lapc t9,L(jtable) PTR_LSA t9,t8,t9,2 +#endif jrc t9 L(jtable): - bc L(aligned) - bc L(r6_unaligned1) - bc L(r6_unaligned2) - bc L(r6_unaligned3) -# ifdef USE_DOUBLE - bc L(r6_unaligned4) - bc L(r6_unaligned5) - bc L(r6_unaligned6) - bc L(r6_unaligned7) -# endif + PTR_BC L(aligned) + PTR_BC L(r6_unaligned1) + PTR_BC L(r6_unaligned2) + PTR_BC L(r6_unaligned3) +#ifdef USE_DOUBLE + PTR_BC L(r6_unaligned4) + PTR_BC L(r6_unaligned5) + PTR_BC L(r6_unaligned6) + PTR_BC L(r6_unaligned7) +#endif #endif /* R6_CODE */ L(aligned): @@ -401,8 +417,8 @@ L(aligned): */ andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */ - beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */ PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */ + beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */ PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */ /* When in the loop we may prefetch with the 'prepare to store' hint, @@ -428,7 +444,6 @@ L(aligned): # if PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE sltu v1,t9,a0 bgtz v1,L(skip_set) - nop PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4) L(skip_set): # else @@ -444,11 +459,16 @@ L(skip_set): #endif L(loop16w): C_LD t0,UNIT(0)(a1) +/* We need to separate out the C_LD instruction here so that it will work + both when it is used by itself and when it is used with the branch + instruction. */ #if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */ + C_LD t1,UNIT(1)(a1) bgtz v1,L(skip_pref) -#endif +#else C_LD t1,UNIT(1)(a1) +#endif #ifdef R6_CODE PREFETCH_FOR_STORE (2, a0) #else @@ -502,8 +522,8 @@ L(skip_pref): C_ST REG6,UNIT(14)(a0) C_ST REG7,UNIT(15)(a0) PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */ - bne a0,a3,L(loop16w) PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */ + bne a0,a3,L(loop16w) move a2,t8 /* Here we have src and dest word-aligned but less than 64-bytes or @@ -517,7 +537,6 @@ L(chkw): andi t8,a2,NSIZEMASK /* Is there a 32-byte/64-byte chunk. */ /* The t8 is the reminder count past 32-bytes */ beq a2,t8,L(chk1w) /* When a2=t8, no 32-byte chunk */ - nop C_LD t0,UNIT(0)(a1) C_LD t1,UNIT(1)(a1) C_LD REG2,UNIT(2)(a1) @@ -546,8 +565,8 @@ L(chkw): */ L(chk1w): andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */ - beq a2,t8,L(lastw) PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */ + beq a2,t8,L(lastw) PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */ /* copying in words (4-byte or 8-byte chunks) */ @@ -555,8 +574,8 @@ L(wordCopy_loop): C_LD REG3,UNIT(0)(a1) PTR_ADDIU a0,a0,UNIT(1) PTR_ADDIU a1,a1,UNIT(1) - bne a0,a3,L(wordCopy_loop) C_ST REG3,UNIT(-1)(a0) + bne a0,a3,L(wordCopy_loop) /* If we have been copying double words, see if we can copy a single word before doing byte copies. We can have, at most, one word to copy. */ @@ -574,17 +593,16 @@ L(lastw): /* Copy the last 8 (or 16) bytes */ L(lastb): - blez a2,L(leave) PTR_ADDU a3,a0,a2 /* a3 is the last dst address */ + blez a2,L(leave) L(lastbloop): lb v1,0(a1) PTR_ADDIU a0,a0,1 PTR_ADDIU a1,a1,1 - bne a0,a3,L(lastbloop) sb v1,-1(a0) + bne a0,a3,L(lastbloop) L(leave): - j ra - nop + jr ra /* We jump here with a memcpy of less than 8 or 16 bytes, depending on whether or not USE_DOUBLE is defined. Instead of just doing byte @@ -625,8 +643,8 @@ L(wcopy_loop): L(unaligned): andi a3,a3,(NSIZE-1) /* copy a3 bytes to align a0/a1 */ + PTR_SUBU a2,a2,a3 /* a2 is the remining bytes count */ beqz a3,L(ua_chk16w) /* if a3=0, it is already aligned */ - PTR_SUBU a2,a2,a3 /* a2 is the remaining bytes count */ C_LDHI v1,UNIT(0)(a1) C_LDLO v1,UNITM1(1)(a1) @@ -644,8 +662,8 @@ L(unaligned): L(ua_chk16w): andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */ - beq a2,t8,L(ua_chkw) /* if a2==t8, no 64-byte/128-byte chunks */ PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */ + beq a2,t8,L(ua_chkw) /* if a2==t8, no 64-byte/128-byte chunks */ PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */ # if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) @@ -664,7 +682,6 @@ L(ua_chk16w): # if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) sltu v1,t9,a0 bgtz v1,L(ua_skip_set) - nop PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4) L(ua_skip_set): # else @@ -676,11 +693,16 @@ L(ua_loop16w): C_LDHI t0,UNIT(0)(a1) C_LDHI t1,UNIT(1)(a1) C_LDHI REG2,UNIT(2)(a1) +/* We need to separate out the C_LDHI instruction here so that it will work + both when it is used by itself and when it is used with the branch + instruction. */ # if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) sltu v1,t9,a0 + C_LDHI REG3,UNIT(3)(a1) bgtz v1,L(ua_skip_pref) -# endif +# else C_LDHI REG3,UNIT(3)(a1) +# endif PREFETCH_FOR_STORE (4, a0) PREFETCH_FOR_STORE (5, a0) L(ua_skip_pref): @@ -731,8 +753,8 @@ L(ua_skip_pref): C_ST REG6,UNIT(14)(a0) C_ST REG7,UNIT(15)(a0) PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */ - bne a0,a3,L(ua_loop16w) PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */ + bne a0,a3,L(ua_loop16w) move a2,t8 /* Here we have src and dest word-aligned but less than 64-bytes or @@ -745,7 +767,6 @@ L(ua_chkw): andi t8,a2,NSIZEMASK /* Is there a 32-byte/64-byte chunk. */ /* t8 is the reminder count past 32-bytes */ beq a2,t8,L(ua_chk1w) /* When a2=t8, no 32-byte chunk */ - nop C_LDHI t0,UNIT(0)(a1) C_LDHI t1,UNIT(1)(a1) C_LDHI REG2,UNIT(2)(a1) @@ -778,8 +799,8 @@ L(ua_chkw): */ L(ua_chk1w): andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */ - beq a2,t8,L(ua_smallCopy) PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */ + beq a2,t8,L(ua_smallCopy) PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */ /* copying in words (4-byte or 8-byte chunks) */ @@ -788,22 +809,21 @@ L(ua_wordCopy_loop): C_LDLO v1,UNITM1(1)(a1) PTR_ADDIU a0,a0,UNIT(1) PTR_ADDIU a1,a1,UNIT(1) - bne a0,a3,L(ua_wordCopy_loop) C_ST v1,UNIT(-1)(a0) + bne a0,a3,L(ua_wordCopy_loop) /* Copy the last 8 (or 16) bytes */ L(ua_smallCopy): - beqz a2,L(leave) PTR_ADDU a3,a0,a2 /* a3 is the last dst address */ + beqz a2,L(leave) L(ua_smallCopy_loop): lb v1,0(a1) PTR_ADDIU a0,a0,1 PTR_ADDIU a1,a1,1 - bne a0,a3,L(ua_smallCopy_loop) sb v1,-1(a0) + bne a0,a3,L(ua_smallCopy_loop) - j ra - nop + jr ra #else /* R6_CODE */ @@ -816,9 +836,9 @@ L(ua_smallCopy_loop): # endif # define R6_UNALIGNED_WORD_COPY(BYTEOFFSET) \ andi REG7, a2, (NSIZE-1);/* REG7 is # of bytes to by bytes. */ \ - beq REG7, a2, L(lastb); /* Check for bytes to copy by word */ \ PTR_SUBU a3, a2, REG7; /* a3 is number of bytes to be copied in */ \ /* (d)word chunks. */ \ + beq REG7, a2, L(lastb); /* Check for bytes to copy by word */ \ move a2, REG7; /* a2 is # of bytes to copy byte by byte */ \ /* after word loop is finished. */ \ PTR_ADDU REG6, a0, a3; /* REG6 is the dst address after loop. */ \ @@ -831,10 +851,9 @@ L(r6_ua_wordcopy##BYTEOFFSET): \ PTR_ADDIU a0, a0, UNIT(1); /* Increment destination pointer. */ \ PTR_ADDIU REG2, REG2, UNIT(1); /* Increment aligned source pointer.*/ \ move t0, t1; /* Move second part of source to first. */ \ - bne a0, REG6,L(r6_ua_wordcopy##BYTEOFFSET); \ C_ST REG3, UNIT(-1)(a0); \ + bne a0, REG6,L(r6_ua_wordcopy##BYTEOFFSET); \ j L(lastb); \ - nop /* We are generating R6 code, the destination is 4 byte aligned and the source is not 4 byte aligned. t8 is 1, 2, or 3 depending on the @@ -859,7 +878,6 @@ L(r6_unaligned7): #endif /* R6_CODE */ .set at - .set reorder END(MEMCPY_NAME) #ifndef ANDROID_CHANGES # ifdef _LIBC diff --git a/sysdeps/mips/memset.S b/sysdeps/mips/memset.S index 96a180732c..833381d73f 100644 --- a/sysdeps/mips/memset.S +++ b/sysdeps/mips/memset.S @@ -82,6 +82,12 @@ # endif #endif +#if __mips_isa_rev > 5 && defined (__mips_micromips) +# define PTR_BC bc16 +#else +# define PTR_BC bc +#endif + /* Using PREFETCH_HINT_PREPAREFORSTORE instead of PREFETCH_STORE or PREFETCH_STORE_STREAMED offers a large performance advantage but PREPAREFORSTORE has some special restrictions to consider. @@ -205,17 +211,16 @@ LEAF(MEMSET_NAME) #endif .set nomips16 - .set noreorder -/* If the size is less than 2*NSIZE (8 or 16), go to L(lastb). Regardless of +/* If the size is less than 4*NSIZE (16 or 32), go to L(lastb). Regardless of size, copy dst pointer to v0 for the return value. */ - slti t2,a2,(2 * NSIZE) - bne t2,zero,L(lastb) + slti t2,a2,(4 * NSIZE) move v0,a0 + bne t2,zero,L(lastb) /* If memset value is not zero, we copy it to all the bytes in a 32 or 64 bit word. */ - beq a1,zero,L(set0) /* If memset value is zero no smear */ PTR_SUBU a3,zero,a0 + beq a1,zero,L(set0) /* If memset value is zero no smear */ nop /* smear byte into 32 or 64 bit word */ @@ -251,26 +256,30 @@ LEAF(MEMSET_NAME) L(set0): #ifndef R6_CODE andi t2,a3,(NSIZE-1) /* word-unaligned address? */ - beq t2,zero,L(aligned) /* t2 is the unalignment count */ PTR_SUBU a2,a2,t2 + beq t2,zero,L(aligned) /* t2 is the unalignment count */ C_STHI a1,0(a0) PTR_ADDU a0,a0,t2 #else /* R6_CODE */ - andi t2,a0,(NSIZE-1) + andi t2,a0,7 +# ifdef __mips_micromips + auipc t9,%pcrel_hi(L(atable)) + addiu t9,t9,%pcrel_lo(L(atable)+4) + PTR_LSA t9,t2,t9,1 +# else lapc t9,L(atable) PTR_LSA t9,t2,t9,2 +# endif jrc t9 L(atable): - bc L(aligned) -# ifdef USE_DOUBLE - bc L(lb7) - bc L(lb6) - bc L(lb5) - bc L(lb4) -# endif - bc L(lb3) - bc L(lb2) - bc L(lb1) + PTR_BC L(aligned) + PTR_BC L(lb7) + PTR_BC L(lb6) + PTR_BC L(lb5) + PTR_BC L(lb4) + PTR_BC L(lb3) + PTR_BC L(lb2) + PTR_BC L(lb1) L(lb7): sb a1,6(a0) L(lb6): @@ -300,8 +309,8 @@ L(aligned): left to store or we would have jumped to L(lastb) earlier in the code. */ #ifdef DOUBLE_ALIGN andi t2,a3,4 - beq t2,zero,L(double_aligned) PTR_SUBU a2,a2,t2 + beq t2,zero,L(double_aligned) sw a1,0(a0) PTR_ADDU a0,a0,t2 L(double_aligned): @@ -313,8 +322,8 @@ L(double_aligned): chunks have been copied. We will loop, incrementing a0 until it equals a3. */ andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */ - beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */ PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */ + beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */ PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */ /* When in the loop we may prefetch with the 'prepare to store' hint, @@ -339,7 +348,6 @@ L(loop16w): && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */ bgtz v1,L(skip_pref) - nop #endif #ifdef R6_CODE PREFETCH_FOR_STORE (2, a0) @@ -366,7 +374,6 @@ L(skip_pref): C_ST a1,UNIT(15)(a0) PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */ bne a0,a3,L(loop16w) - nop move a2,t8 /* Here we have dest word-aligned but less than 64-bytes or 128 bytes to go. @@ -376,7 +383,6 @@ L(chkw): andi t8,a2,NSIZEMASK /* is there a 32-byte/64-byte chunk. */ /* the t8 is the reminder count past 32-bytes */ beq a2,t8,L(chk1w)/* when a2==t8, no 32-byte chunk */ - nop C_ST a1,UNIT(0)(a0) C_ST a1,UNIT(1)(a0) C_ST a1,UNIT(2)(a0) @@ -394,30 +400,28 @@ L(chkw): been copied. We will loop, incrementing a0 until a0 equals a3. */ L(chk1w): andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */ - beq a2,t8,L(lastb) PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */ + beq a2,t8,L(lastb) PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */ /* copying in words (4-byte or 8 byte chunks) */ L(wordCopy_loop): PTR_ADDIU a0,a0,UNIT(1) - bne a0,a3,L(wordCopy_loop) C_ST a1,UNIT(-1)(a0) + bne a0,a3,L(wordCopy_loop) /* Copy the last 8 (or 16) bytes */ L(lastb): - blez a2,L(leave) PTR_ADDU a3,a0,a2 /* a3 is the last dst address */ + blez a2,L(leave) L(lastbloop): PTR_ADDIU a0,a0,1 - bne a0,a3,L(lastbloop) sb a1,-1(a0) + bne a0,a3,L(lastbloop) L(leave): - j ra - nop + jr ra .set at - .set reorder END(MEMSET_NAME) #ifndef ANDROID_CHANGES # ifdef _LIBC diff --git a/sysdeps/mips/mips32/crtn.S b/sysdeps/mips/mips32/crtn.S index dcca552a70..cc8cd3676e 100644 --- a/sysdeps/mips/mips32/crtn.S +++ b/sysdeps/mips/mips32/crtn.S @@ -40,18 +40,10 @@ .section .init,"ax",@progbits lw $31,28($sp) - .set noreorder - .set nomacro - j $31 addiu $sp,$sp,32 - .set macro - .set reorder + jr $31 .section .fini,"ax",@progbits lw $31,28($sp) - .set noreorder - .set nomacro - j $31 addiu $sp,$sp,32 - .set macro - .set reorder + jr $31 diff --git a/sysdeps/mips/mips64/__longjmp.c b/sysdeps/mips/mips64/__longjmp.c index 358e666f18..3183d15e6d 100644 --- a/sysdeps/mips/mips64/__longjmp.c +++ b/sysdeps/mips/mips64/__longjmp.c @@ -87,7 +87,7 @@ __longjmp (__jmp_buf env_arg, int val_arg) else asm volatile ("move $2, %0" : : "r" (val)); - asm volatile ("j $31"); + asm volatile ("jr $31"); /* Avoid `volatile function does return' warnings. */ for (;;); diff --git a/sysdeps/mips/mips64/add_n.S b/sysdeps/mips/mips64/add_n.S index 1c9994bf7c..0abb0a81a4 100644 --- a/sysdeps/mips/mips64/add_n.S +++ b/sysdeps/mips/mips64/add_n.S @@ -37,16 +37,13 @@ ENTRY (__mpn_add_n) #ifdef __PIC__ SETUP_GP /* ??? unused */ #endif - .set noreorder - .set nomacro - ld $10,0($5) ld $11,0($6) daddiu $7,$7,-1 and $9,$7,4-1 # number of limbs in first loop - beq $9,$0,L(L0) # if multiple of 4 limbs, skip first loop move $2,$0 + beq $9,$0,L(L0) # if multiple of 4 limbs, skip first loop dsubu $7,$7,$9 @@ -64,11 +61,10 @@ L(Loop0): daddiu $9,$9,-1 daddiu $6,$6,8 move $10,$12 move $11,$13 - bne $9,$0,L(Loop0) daddiu $4,$4,8 + bne $9,$0,L(Loop0) L(L0): beq $7,$0,L(Lend) - nop L(Loop): daddiu $7,$7,-4 @@ -111,15 +107,15 @@ L(Loop): daddiu $7,$7,-4 daddiu $5,$5,32 daddiu $6,$6,32 - bne $7,$0,L(Loop) daddiu $4,$4,32 + bne $7,$0,L(Loop) L(Lend): daddu $11,$11,$2 sltu $8,$11,$2 daddu $11,$10,$11 sltu $2,$11,$10 sd $11,0($4) - j $31 or $2,$2,$8 + jr $31 END (__mpn_add_n) diff --git a/sysdeps/mips/mips64/addmul_1.S b/sysdeps/mips/mips64/addmul_1.S index 4d065bc66a..2666ad64a3 100644 --- a/sysdeps/mips/mips64/addmul_1.S +++ b/sysdeps/mips/mips64/addmul_1.S @@ -36,9 +36,6 @@ ENTRY (__mpn_addmul_1) #ifdef PIC SETUP_GP /* ??? unused */ #endif - .set noreorder - .set nomacro - # warm up phase 0 ld $8,0($5) @@ -52,12 +49,12 @@ ENTRY (__mpn_addmul_1) #endif daddiu $6,$6,-1 - beq $6,$0,L(LC0) move $2,$0 # zero cy2 + beq $6,$0,L(LC0) daddiu $6,$6,-1 - beq $6,$0,L(LC1) ld $8,0($5) # load new s1 limb as early as possible + beq $6,$0,L(LC1) L(Loop): ld $10,0($4) #if __mips_isa_rev < 6 @@ -83,8 +80,8 @@ L(Loop): ld $10,0($4) daddu $2,$2,$10 sd $3,0($4) daddiu $4,$4,8 - bne $6,$0,L(Loop) daddu $2,$9,$2 # add high product limb and carry from addition + bne $6,$0,L(Loop) # cool down phase 1 L(LC1): ld $10,0($4) @@ -125,7 +122,7 @@ L(LC0): ld $10,0($4) sltu $10,$3,$10 daddu $2,$2,$10 sd $3,0($4) - j $31 daddu $2,$9,$2 # add high product limb and carry from addition + jr $31 END (__mpn_addmul_1) diff --git a/sysdeps/mips/mips64/lshift.S b/sysdeps/mips/mips64/lshift.S index 988b765487..615060a401 100644 --- a/sysdeps/mips/mips64/lshift.S +++ b/sysdeps/mips/mips64/lshift.S @@ -36,9 +36,6 @@ ENTRY (__mpn_lshift) #ifdef __PIC__ SETUP_GP /* ??? unused */ #endif - .set noreorder - .set nomacro - dsll $2,$6,3 daddu $5,$5,$2 # make r5 point at end of src ld $10,-8($5) # load first limb @@ -46,8 +43,8 @@ ENTRY (__mpn_lshift) daddu $4,$4,$2 # make r4 point at end of res daddiu $6,$6,-1 and $9,$6,4-1 # number of limbs in first loop - beq $9,$0,L(L0) # if multiple of 4 limbs, skip first loop dsrl $2,$10,$13 # compute function result + beq $9,$0,L(L0) # if multiple of 4 limbs, skip first loop dsubu $6,$6,$9 @@ -59,11 +56,10 @@ L(Loop0): ld $3,-16($5) dsrl $12,$3,$13 move $10,$3 or $8,$11,$12 - bne $9,$0,L(Loop0) sd $8,0($4) + bne $9,$0,L(Loop0) L(L0): beq $6,$0,L(Lend) - nop L(Loop): ld $3,-16($5) daddiu $4,$4,-32 @@ -91,10 +87,10 @@ L(Loop): ld $3,-16($5) daddiu $5,$5,-32 or $8,$14,$9 - bgtz $6,L(Loop) sd $8,0($4) + bgtz $6,L(Loop) L(Lend): dsll $8,$10,$7 - j $31 sd $8,-8($4) + jr $31 END (__mpn_lshift) diff --git a/sysdeps/mips/mips64/mul_1.S b/sysdeps/mips/mips64/mul_1.S index f48415ea5d..6461582eb8 100644 --- a/sysdeps/mips/mips64/mul_1.S +++ b/sysdeps/mips/mips64/mul_1.S @@ -37,9 +37,6 @@ ENTRY (__mpn_mul_1) #ifdef __PIC__ SETUP_GP /* ??? unused */ #endif - .set noreorder - .set nomacro - # warm up phase 0 ld $8,0($5) @@ -53,12 +50,12 @@ ENTRY (__mpn_mul_1) #endif daddiu $6,$6,-1 - beq $6,$0,L(LC0) move $2,$0 # zero cy2 + beq $6,$0,L(LC0) daddiu $6,$6,-1 - beq $6,$0,L(LC1) ld $8,0($5) # load new s1 limb as early as possible + beq $6,$0,L(LC1) #if __mips_isa_rev < 6 L(Loop): mflo $10 @@ -80,8 +77,8 @@ L(Loop): move $10,$11 sltu $2,$10,$2 # carry from previous addition -> $2 sd $10,0($4) daddiu $4,$4,8 - bne $6,$0,L(Loop) daddu $2,$9,$2 # add high product limb and carry from addition + bne $6,$0,L(Loop) # cool down phase 1 #if __mips_isa_rev < 6 @@ -114,7 +111,7 @@ L(LC0): move $10,$11 daddu $10,$10,$2 sltu $2,$10,$2 sd $10,0($4) - j $31 daddu $2,$9,$2 # add high product limb and carry from addition + jr $31 END (__mpn_mul_1) diff --git a/sysdeps/mips/mips64/n32/crtn.S b/sysdeps/mips/mips64/n32/crtn.S index e353dbf2db..7fc6d61f08 100644 --- a/sysdeps/mips/mips64/n32/crtn.S +++ b/sysdeps/mips/mips64/n32/crtn.S @@ -41,19 +41,11 @@ .section .init,"ax",@progbits ld $31,8($sp) ld $28,0($sp) - .set noreorder - .set nomacro - j $31 addiu $sp,$sp,16 - .set macro - .set reorder + jr $31 .section .fini,"ax",@progbits ld $31,8($sp) ld $28,0($sp) - .set noreorder - .set nomacro - j $31 addiu $sp,$sp,16 - .set macro - .set reorder + jr $31 diff --git a/sysdeps/mips/mips64/n64/crtn.S b/sysdeps/mips/mips64/n64/crtn.S index 8abbf86cc6..8c8970c0fa 100644 --- a/sysdeps/mips/mips64/n64/crtn.S +++ b/sysdeps/mips/mips64/n64/crtn.S @@ -41,19 +41,11 @@ .section .init,"ax",@progbits ld $31,8($sp) ld $28,0($sp) - .set noreorder - .set nomacro - j $31 daddiu $sp,$sp,16 - .set macro - .set reorder + jr $31 .section .fini,"ax",@progbits ld $31,8($sp) ld $28,0($sp) - .set noreorder - .set nomacro - j $31 daddiu $sp,$sp,16 - .set macro - .set reorder + jr $31 diff --git a/sysdeps/mips/mips64/rshift.S b/sysdeps/mips/mips64/rshift.S index 2b43aa25ad..0496da6cbe 100644 --- a/sysdeps/mips/mips64/rshift.S +++ b/sysdeps/mips/mips64/rshift.S @@ -36,15 +36,12 @@ ENTRY (__mpn_rshift) #ifdef __PIC__ SETUP_GP /* ??? unused */ #endif - .set noreorder - .set nomacro - ld $10,0($5) # load first limb dsubu $13,$0,$7 daddiu $6,$6,-1 and $9,$6,4-1 # number of limbs in first loop - beq $9,$0,L(L0) # if multiple of 4 limbs, skip first loop dsll $2,$10,$13 # compute function result + beq $9,$0,L(L0) # if multiple of 4 limbs, skip first loop dsubu $6,$6,$9 @@ -56,11 +53,10 @@ L(Loop0): ld $3,8($5) dsll $12,$3,$13 move $10,$3 or $8,$11,$12 - bne $9,$0,L(Loop0) sd $8,-8($4) + bne $9,$0,L(Loop0) L(L0): beq $6,$0,L(Lend) - nop L(Loop): ld $3,8($5) daddiu $4,$4,32 @@ -88,10 +84,10 @@ L(Loop): ld $3,8($5) daddiu $5,$5,32 or $8,$14,$9 - bgtz $6,L(Loop) sd $8,-8($4) + bgtz $6,L(Loop) L(Lend): dsrl $8,$10,$7 - j $31 sd $8,0($4) + jr $31 END (__mpn_rshift) diff --git a/sysdeps/mips/mips64/sub_n.S b/sysdeps/mips/mips64/sub_n.S index 230132c662..30a0f87592 100644 --- a/sysdeps/mips/mips64/sub_n.S +++ b/sysdeps/mips/mips64/sub_n.S @@ -37,16 +37,13 @@ ENTRY (__mpn_sub_n) #ifdef __PIC__ SETUP_GP /* ??? unused */ #endif - .set noreorder - .set nomacro - ld $10,0($5) ld $11,0($6) daddiu $7,$7,-1 and $9,$7,4-1 # number of limbs in first loop - beq $9,$0,L(L0) # if multiple of 4 limbs, skip first loop move $2,$0 + beq $9,$0,L(L0) # if multiple of 4 limbs, skip first loop dsubu $7,$7,$9 @@ -64,11 +61,10 @@ L(Loop0): daddiu $9,$9,-1 daddiu $6,$6,8 move $10,$12 move $11,$13 - bne $9,$0,L(Loop0) daddiu $4,$4,8 + bne $9,$0,L(Loop0) L(L0): beq $7,$0,L(Lend) - nop L(Loop): daddiu $7,$7,-4 @@ -111,15 +107,15 @@ L(Loop): daddiu $7,$7,-4 daddiu $5,$5,32 daddiu $6,$6,32 - bne $7,$0,L(Loop) daddiu $4,$4,32 + bne $7,$0,L(Loop) L(Lend): daddu $11,$11,$2 sltu $8,$11,$2 dsubu $11,$10,$11 sltu $2,$10,$11 sd $11,0($4) - j $31 or $2,$2,$8 + jr $31 END (__mpn_sub_n) diff --git a/sysdeps/mips/mips64/submul_1.S b/sysdeps/mips/mips64/submul_1.S index 618c64a97f..6b0a63919f 100644 --- a/sysdeps/mips/mips64/submul_1.S +++ b/sysdeps/mips/mips64/submul_1.S @@ -37,9 +37,6 @@ ENTRY (__mpn_submul_1) #ifdef __PIC__ SETUP_GP /* ??? unused */ #endif - .set noreorder - .set nomacro - # warm up phase 0 ld $8,0($5) @@ -53,12 +50,12 @@ ENTRY (__mpn_submul_1) #endif daddiu $6,$6,-1 - beq $6,$0,L(LC0) move $2,$0 # zero cy2 + beq $6,$0,L(LC0) daddiu $6,$6,-1 - beq $6,$0,L(LC1) ld $8,0($5) # load new s1 limb as early as possible + beq $6,$0,L(LC1) L(Loop): ld $10,0($4) #if __mips_isa_rev < 6 @@ -84,8 +81,8 @@ L(Loop): ld $10,0($4) daddu $2,$2,$10 sd $3,0($4) daddiu $4,$4,8 - bne $6,$0,L(Loop) daddu $2,$9,$2 # add high product limb and carry from addition + bne $6,$0,L(Loop) # cool down phase 1 L(LC1): ld $10,0($4) @@ -126,7 +123,7 @@ L(LC0): ld $10,0($4) sgtu $10,$3,$10 daddu $2,$2,$10 sd $3,0($4) - j $31 daddu $2,$9,$2 # add high product limb and carry from addition + jr $31 END (__mpn_submul_1) diff --git a/sysdeps/mips/mul_1.S b/sysdeps/mips/mul_1.S index 6e1af16d41..0f97464fe4 100644 --- a/sysdeps/mips/mul_1.S +++ b/sysdeps/mips/mul_1.S @@ -31,12 +31,9 @@ along with the GNU MP Library. If not, see .option pic2 #endif ENTRY (__mpn_mul_1) - .set noreorder #ifdef __PIC__ .cpload t9 #endif - .set nomacro - /* warm up phase 0 */ lw $8,0($5) @@ -50,12 +47,12 @@ ENTRY (__mpn_mul_1) #endif addiu $6,$6,-1 - beq $6,$0,L(LC0) move $2,$0 /* zero cy2 */ + beq $6,$0,L(LC0) addiu $6,$6,-1 - beq $6,$0,L(LC1) lw $8,0($5) /* load new s1 limb as early as possible */ + beq $6,$0,L(LC1) #if __mips_isa_rev < 6 @@ -78,8 +75,8 @@ L(Loop): move $10,$11 sltu $2,$10,$2 /* carry from previous addition -> $2 */ sw $10,0($4) addiu $4,$4,4 - bne $6,$0,L(Loop) /* should be "bnel" */ addu $2,$9,$2 /* add high product limb and carry from addition */ + bne $6,$0,L(Loop) /* should be "bnel" */ /* cool down phase 1 */ #if __mips_isa_rev < 6 @@ -112,6 +109,6 @@ L(LC0): move $10,$11 addu $10,$10,$2 sltu $2,$10,$2 sw $10,0($4) - j $31 addu $2,$9,$2 /* add high product limb and carry from addition */ + jr $31 END (__mpn_mul_1) diff --git a/sysdeps/mips/rshift.S b/sysdeps/mips/rshift.S index 81db963750..255e94e564 100644 --- a/sysdeps/mips/rshift.S +++ b/sysdeps/mips/rshift.S @@ -30,18 +30,15 @@ along with the GNU MP Library. If not, see .option pic2 #endif ENTRY (__mpn_rshift) - .set noreorder #ifdef __PIC__ .cpload t9 #endif - .set nomacro - lw $10,0($5) /* load first limb */ subu $13,$0,$7 addiu $6,$6,-1 and $9,$6,4-1 /* number of limbs in first loop */ + sll $2,$10,$13 /* compute function result */ beq $9,$0,L(L0) /* if multiple of 4 limbs, skip first loop*/ - sll $2,$10,$13 /* compute function result */ subu $6,$6,$9 @@ -53,11 +50,10 @@ L(Loop0): lw $3,4($5) sll $12,$3,$13 move $10,$3 or $8,$11,$12 + sw $8,-4($4) bne $9,$0,L(Loop0) - sw $8,-4($4) L(L0): beq $6,$0,L(Lend) - nop L(Loop): lw $3,4($5) addiu $4,$4,16 @@ -85,10 +81,10 @@ L(Loop): lw $3,4($5) addiu $5,$5,16 or $8,$14,$9 + sw $8,-4($4) bgtz $6,L(Loop) - sw $8,-4($4) L(Lend): srl $8,$10,$7 - j $31 sw $8,0($4) + jr $31 END (__mpn_rshift) diff --git a/sysdeps/mips/sub_n.S b/sysdeps/mips/sub_n.S index 39f1888fe4..900658c3ac 100644 --- a/sysdeps/mips/sub_n.S +++ b/sysdeps/mips/sub_n.S @@ -31,19 +31,16 @@ along with the GNU MP Library. If not, see .option pic2 #endif ENTRY (__mpn_sub_n) - .set noreorder #ifdef __PIC__ .cpload t9 #endif - .set nomacro - lw $10,0($5) lw $11,0($6) addiu $7,$7,-1 and $9,$7,4-1 /* number of limbs in first loop */ - beq $9,$0,L(L0) /* if multiple of 4 limbs, skip first loop */ move $2,$0 + beq $9,$0,L(L0) /* if multiple of 4 limbs, skip first loop */ subu $7,$7,$9 @@ -61,11 +58,10 @@ L(Loop0): addiu $9,$9,-1 addiu $6,$6,4 move $10,$12 move $11,$13 - bne $9,$0,L(Loop0) addiu $4,$4,4 + bne $9,$0,L(Loop0) L(L0): beq $7,$0,L(Lend) - nop L(Loop): addiu $7,$7,-4 @@ -108,14 +104,14 @@ L(Loop): addiu $7,$7,-4 addiu $5,$5,16 addiu $6,$6,16 - bne $7,$0,L(Loop) addiu $4,$4,16 + bne $7,$0,L(Loop) L(Lend): addu $11,$11,$2 sltu $8,$11,$2 subu $11,$10,$11 sltu $2,$10,$11 sw $11,0($4) - j $31 or $2,$2,$8 + jr $31 END (__mpn_sub_n) diff --git a/sysdeps/mips/submul_1.S b/sysdeps/mips/submul_1.S index c2223664c5..7ac93b12ec 100644 --- a/sysdeps/mips/submul_1.S +++ b/sysdeps/mips/submul_1.S @@ -31,12 +31,9 @@ along with the GNU MP Library. If not, see .option pic2 #endif ENTRY (__mpn_submul_1) - .set noreorder #ifdef __PIC__ .cpload t9 #endif - .set nomacro - /* warm up phase 0 */ lw $8,0($5) @@ -50,12 +47,12 @@ ENTRY (__mpn_submul_1) #endif addiu $6,$6,-1 - beq $6,$0,L(LC0) move $2,$0 /* zero cy2 */ + beq $6,$0,L(LC0) addiu $6,$6,-1 - beq $6,$0,L(LC1) lw $8,0($5) /* load new s1 limb as early as possible */ + beq $6,$0,L(LC1) L(Loop): lw $10,0($4) #if __mips_isa_rev < 6 @@ -81,8 +78,8 @@ L(Loop): lw $10,0($4) addu $2,$2,$10 sw $3,0($4) addiu $4,$4,4 - bne $6,$0,L(Loop) /* should be "bnel" */ addu $2,$9,$2 /* add high product limb and carry from addition */ + bne $6,$0,L(Loop) /* should be "bnel" */ /* cool down phase 1 */ L(LC1): lw $10,0($4) @@ -123,6 +120,6 @@ L(LC0): lw $10,0($4) sgtu $10,$3,$10 addu $2,$2,$10 sw $3,0($4) - j $31 addu $2,$9,$2 /* add high product limb and carry from addition */ + jr $31 END (__mpn_submul_1) diff --git a/sysdeps/mips/sys/asm.h b/sysdeps/mips/sys/asm.h index d40ca751e4..73b2be554e 100644 --- a/sysdeps/mips/sys/asm.h +++ b/sysdeps/mips/sys/asm.h @@ -71,23 +71,21 @@ .set reorder /* Set gp when not at 1st instruction */ # define SETUP_GPX(r) \ - .set noreorder; \ move r, $31; /* Save old ra. */ \ bal 10f; /* Find addr of cpload. */ \ - nop; \ 10: \ + .set noreorder; \ .cpload $31; \ - move $31, r; \ - .set reorder + .set reorder; \ + move $31, r; # define SETUP_GPX_L(r, l) \ - .set noreorder; \ move r, $31; /* Save old ra. */ \ bal l; /* Find addr of cpload. */ \ - nop; \ l: \ + .set noreorder; \ .cpload $31; \ - move $31, r; \ - .set reorder + .set reorder; \ + move $31, r; # define SAVE_GP(x) \ .cprestore x /* Save gp trigger t9/jalr conversion. */ # define SETUP_GP64(a, b) @@ -108,20 +106,14 @@ l: \ .cpsetup $25, gpoffset, proc # define SETUP_GPX64(cp_reg, ra_save) \ move ra_save, $31; /* Save old ra. */ \ - .set noreorder; \ bal 10f; /* Find addr of .cpsetup. */ \ - nop; \ 10: \ - .set reorder; \ .cpsetup $31, cp_reg, 10b; \ move $31, ra_save # define SETUP_GPX64_L(cp_reg, ra_save, l) \ move ra_save, $31; /* Save old ra. */ \ - .set noreorder; \ bal l; /* Find addr of .cpsetup. */ \ - nop; \ l: \ - .set reorder; \ .cpsetup $31, cp_reg, l; \ move $31, ra_save # define RESTORE_GP64 \ diff --git a/sysdeps/unix/mips/mips32/sysdep.h b/sysdeps/unix/mips/mips32/sysdep.h index e09e4be5b0..b4c49ff306 100644 --- a/sysdeps/unix/mips/mips32/sysdep.h +++ b/sysdeps/unix/mips/mips32/sysdep.h @@ -38,18 +38,14 @@ L(syse1): #else #define PSEUDO(name, syscall_name, args) \ - .set noreorder; \ .set nomips16; \ .align 2; \ cfi_startproc; \ 99: j __syscall_error; \ - nop; \ cfi_endproc; \ ENTRY(name) \ - .set noreorder; \ li v0, SYS_ify(syscall_name); \ syscall; \ - .set reorder; \ bne a3, zero, 99b; \ L(syse1): #endif diff --git a/sysdeps/unix/mips/mips64/sysdep.h b/sysdeps/unix/mips/mips64/sysdep.h index 206569357a..fb21eaca27 100644 --- a/sysdeps/unix/mips/mips64/sysdep.h +++ b/sysdeps/unix/mips/mips64/sysdep.h @@ -45,18 +45,14 @@ L(syse1): #else #define PSEUDO(name, syscall_name, args) \ - .set noreorder; \ .align 2; \ .set nomips16; \ cfi_startproc; \ 99: j __syscall_error; \ - nop; \ cfi_endproc; \ ENTRY(name) \ - .set noreorder; \ li v0, SYS_ify(syscall_name); \ syscall; \ - .set reorder; \ bne a3, zero, 99b; \ L(syse1): #endif diff --git a/sysdeps/unix/mips/sysdep.h b/sysdeps/unix/mips/sysdep.h index 5f7706b182..1c962f701c 100644 --- a/sysdeps/unix/mips/sysdep.h +++ b/sysdeps/unix/mips/sysdep.h @@ -48,7 +48,6 @@ .align 2; \ ENTRY(name) \ .set nomips16; \ - .set noreorder; \ li v0, SYS_ify(syscall_name); \ syscall @@ -61,7 +60,6 @@ .align 2; \ ENTRY(name) \ .set nomips16; \ - .set noreorder; \ li v0, SYS_ify(syscall_name); \ syscall diff --git a/sysdeps/unix/sysv/linux/mips/mips32/sysdep.h b/sysdeps/unix/sysv/linux/mips/mips32/sysdep.h index 83ccfb08af..7f22da53f4 100644 --- a/sysdeps/unix/sysv/linux/mips/mips32/sysdep.h +++ b/sysdeps/unix/sysv/linux/mips/mips32/sysdep.h @@ -140,10 +140,8 @@ union __mips_syscall_return register long int __v0 asm ("$2"); \ register long int __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set reorder" \ : "=r" (__v0), "=r" (__a3) \ : input \ : __SYSCALL_CLOBBERS); \ @@ -164,10 +162,8 @@ union __mips_syscall_return register long int __a0 asm ("$4") = _arg1; \ register long int __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set reorder" \ : "=r" (__v0), "=r" (__a3) \ : input, "r" (__a0) \ : __SYSCALL_CLOBBERS); \ @@ -190,10 +186,8 @@ union __mips_syscall_return register long int __a1 asm ("$5") = _arg2; \ register long int __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "=r" (__a3) \ : input, "r" (__a0), "r" (__a1) \ : __SYSCALL_CLOBBERS); \ @@ -219,10 +213,8 @@ union __mips_syscall_return register long int __a2 asm ("$6") = _arg3; \ register long int __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "=r" (__a3) \ : input, "r" (__a0), "r" (__a1), "r" (__a2) \ : __SYSCALL_CLOBBERS); \ @@ -249,10 +241,8 @@ union __mips_syscall_return register long int __a2 asm ("$6") = _arg3; \ register long int __a3 asm ("$7") = _arg4; \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "+r" (__a3) \ : input, "r" (__a0), "r" (__a1), "r" (__a2) \ : __SYSCALL_CLOBBERS); \ diff --git a/sysdeps/unix/sysv/linux/mips/mips64/sysdep.h b/sysdeps/unix/sysv/linux/mips/mips64/sysdep.h index 78044d669d..ffb7c54301 100644 --- a/sysdeps/unix/sysv/linux/mips/mips64/sysdep.h +++ b/sysdeps/unix/sysv/linux/mips/mips64/sysdep.h @@ -95,10 +95,8 @@ register __syscall_arg_t __v0 asm ("$2"); \ register __syscall_arg_t __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set reorder" \ : "=r" (__v0), "=r" (__a3) \ : input \ : __SYSCALL_CLOBBERS); \ @@ -119,10 +117,8 @@ register __syscall_arg_t __a0 asm ("$4") = _arg1; \ register __syscall_arg_t __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set reorder" \ : "=r" (__v0), "=r" (__a3) \ : input, "r" (__a0) \ : __SYSCALL_CLOBBERS); \ @@ -145,10 +141,8 @@ register __syscall_arg_t __a1 asm ("$5") = _arg2; \ register __syscall_arg_t __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "=r" (__a3) \ : input, "r" (__a0), "r" (__a1) \ : __SYSCALL_CLOBBERS); \ @@ -173,10 +167,8 @@ register __syscall_arg_t __a2 asm ("$6") = _arg3; \ register __syscall_arg_t __a3 asm ("$7"); \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "=r" (__a3) \ : input, "r" (__a0), "r" (__a1), "r" (__a2) \ : __SYSCALL_CLOBBERS); \ @@ -203,10 +195,8 @@ register __syscall_arg_t __a2 asm ("$6") = _arg3; \ register __syscall_arg_t __a3 asm ("$7") = _arg4; \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "+r" (__a3) \ : input, "r" (__a0), "r" (__a1), "r" (__a2) \ : __SYSCALL_CLOBBERS); \ @@ -235,10 +225,8 @@ register __syscall_arg_t __a3 asm ("$7") = _arg4; \ register __syscall_arg_t __a4 asm ("$8") = _arg5; \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "+r" (__a3) \ : input, "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4) \ : __SYSCALL_CLOBBERS); \ @@ -269,10 +257,8 @@ register __syscall_arg_t __a4 asm ("$8") = _arg5; \ register __syscall_arg_t __a5 asm ("$9") = _arg6; \ __asm__ volatile ( \ - ".set\tnoreorder\n\t" \ v0_init \ "syscall\n\t" \ - ".set\treorder" \ : "=r" (__v0), "+r" (__a3) \ : input, "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), \ "r" (__a5) \ From patchwork Wed Jun 18 14:33:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jovan Dmitrovic X-Patchwork-Id: 114677 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 619E53816227 for ; Wed, 18 Jun 2025 14:39:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 619E53816227 Authentication-Results: sourceware.org; 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If l_mach isn't zero-initialized, we may get dynamic linking failures due to incompatible FP ABIs. Similar issue may arise or is already present on other platforms. Reported-by: Sandra Loosemore Signed-off-by: Jovan Dmitrović --- elf/rtld.c | 1 + 1 file changed, 1 insertion(+) -- 2.34.1 diff --git a/elf/rtld.c b/elf/rtld.c index 099c447e80..ad64450477 100644 --- a/elf/rtld.c +++ b/elf/rtld.c @@ -531,6 +531,7 @@ _dl_start (void *arg) do not have to use the temporary bootstrap_map. Global variables are initialized to zero by default. */ #ifndef DONT_USE_BOOTSTRAP_MAP + bootstrap_map.l_mach = (struct link_map_machine) {}; # ifdef HAVE_BUILTIN_MEMSET __builtin_memset (bootstrap_map.l_info, '\0', sizeof (bootstrap_map.l_info)); # else From patchwork Wed Jun 18 14:33:44 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jovan Dmitrovic X-Patchwork-Id: 114671 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E728D381621C for ; Wed, 18 Jun 2025 14:35:02 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazlp170100001.outbound.protection.outlook.com [IPv6:2a01:111:f403:c200::1]) by sourceware.org (Postfix) with ESMTPS id 5807638734AC for ; Wed, 18 Jun 2025 14:34:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5807638734AC Authentication-Results: sourceware.org; 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Added -O2 to the Makefile to ensure that assembly sources have their delay slots filled. 2. Also move the no-reorder directive into the PIC section of the setjmp code. Cherry-picked 4e451260675b2e54535eafc2df35d92653acd084 from https://github.com/MIPS/glibc Signed-off-by: Andrew Bennett Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic Signed-off-by: Jovan Dmitrović --- sysdeps/mips/Makefile | 2 ++ sysdeps/mips/bsd-setjmp.S | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) -- 2.34.1 diff --git a/sysdeps/mips/Makefile b/sysdeps/mips/Makefile index d189973aa0..17ddc2a97c 100644 --- a/sysdeps/mips/Makefile +++ b/sysdeps/mips/Makefile @@ -18,9 +18,11 @@ CPPFLAGS-crtn.S += $(pic-ccflag) endif ASFLAGS-.os += $(pic-ccflag) + # libc.a and libc_p.a must be compiled with -fPIE/-fpie for static PIE. ASFLAGS-.o += $(pie-default) ASFLAGS-.op += $(pie-default) +ASFLAGS += -O2 ifeq ($(subdir),elf) diff --git a/sysdeps/mips/bsd-setjmp.S b/sysdeps/mips/bsd-setjmp.S index b8f5ef6ca7..4d638216d2 100644 --- a/sysdeps/mips/bsd-setjmp.S +++ b/sysdeps/mips/bsd-setjmp.S @@ -28,8 +28,8 @@ .option pic2 #endif ENTRY (setjmp) - .set noreorder #ifdef __PIC__ + .set noreorder .cpload t9 .set reorder la t9, C_SYMBOL_NAME (__sigsetjmp) From patchwork Wed Jun 18 14:33:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jovan Dmitrovic X-Patchwork-Id: 114678 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1B9903816208 for ; Wed, 18 Jun 2025 14:41:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1B9903816208 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.a=rsa-sha256 header.s=selector1 header.b=f1T9i5Mh X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazlp170100001.outbound.protection.outlook.com [IPv6:2a01:111:f403:c200::1]) by sourceware.org (Postfix) with ESMTPS id 3E24F3884D63 for ; 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Cherry-picked 6b74133706246af94b71e4154e4ca09482828c9f from https://github.com/MIPS/glibc Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic Signed-off-by: Jovan Dmitrović --- sysdeps/mips/memcpy.S | 886 ------------------------------------------ sysdeps/mips/memcpy.c | 415 ++++++++++++++++++++ sysdeps/mips/memset.S | 430 -------------------- sysdeps/mips/memset.c | 188 +++++++++ 4 files changed, 603 insertions(+), 1316 deletions(-) delete mode 100644 sysdeps/mips/memcpy.S create mode 100644 sysdeps/mips/memcpy.c delete mode 100644 sysdeps/mips/memset.S create mode 100644 sysdeps/mips/memset.c -- 2.34.1 diff --git a/sysdeps/mips/memcpy.S b/sysdeps/mips/memcpy.S deleted file mode 100644 index 8736cfbec6..0000000000 --- a/sysdeps/mips/memcpy.S +++ /dev/null @@ -1,886 +0,0 @@ -/* Copyright (C) 2012-2025 Free Software Foundation, Inc. - This file is part of the GNU C Library. - - The GNU C Library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - The GNU C Library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with the GNU C Library. If not, see - . */ - -#ifdef ANDROID_CHANGES -# include "machine/asm.h" -# include "machine/regdef.h" -# define USE_MEMMOVE_FOR_OVERLAP -# define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED -# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE -#elif _LIBC -# include -# include -# include -# define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED -# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE -#elif defined _COMPILING_NEWLIB -# include "machine/asm.h" -# include "machine/regdef.h" -# define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED -# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE -#else -# include -# include -#endif - -#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -# ifndef DISABLE_PREFETCH -# define USE_PREFETCH -# endif -#endif - -#if defined(_MIPS_SIM) && ((_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32)) -# ifndef DISABLE_DOUBLE -# define USE_DOUBLE -# endif -#endif - -/* Some asm.h files do not have the L macro definition. */ -#ifndef L -# if _MIPS_SIM == _ABIO32 -# define L(label) $L ## label -# else -# define L(label) .L ## label -# endif -#endif - -/* Some asm.h files do not have the PTR_ADDIU macro definition. */ -#ifndef PTR_ADDIU -# ifdef USE_DOUBLE -# define PTR_ADDIU daddiu -# else -# define PTR_ADDIU addiu -# endif -#endif - -/* Some asm.h files do not have the PTR_SRA macro definition. */ -#ifndef PTR_SRA -# ifdef USE_DOUBLE -# define PTR_SRA dsra -# else -# define PTR_SRA sra -# endif -#endif - -/* New R6 instructions that may not be in asm.h. */ -#ifndef PTR_LSA -# if _MIPS_SIM == _ABI64 -# define PTR_LSA dlsa -# else -# define PTR_LSA lsa -# endif -#endif - -#if __mips_isa_rev > 5 && defined (__mips_micromips) -# define PTR_BC bc16 -#else -# define PTR_BC bc -#endif - -/* - * Using PREFETCH_HINT_LOAD_STREAMED instead of PREFETCH_LOAD on load - * prefetches appear to offer a slight performance advantage. - * - * Using PREFETCH_HINT_PREPAREFORSTORE instead of PREFETCH_STORE - * or PREFETCH_STORE_STREAMED offers a large performance advantage - * but PREPAREFORSTORE has some special restrictions to consider. - * - * Prefetch with the 'prepare for store' hint does not copy a memory - * location into the cache, it just allocates a cache line and zeros - * it out. This means that if you do not write to the entire cache - * line before writing it out to memory some data will get zero'ed out - * when the cache line is written back to memory and data will be lost. - * - * Also if you are using this memcpy to copy overlapping buffers it may - * not behave correctly when using the 'prepare for store' hint. If you - * use the 'prepare for store' prefetch on a memory area that is in the - * memcpy source (as well as the memcpy destination), then you will get - * some data zero'ed out before you have a chance to read it and data will - * be lost. - * - * If you are going to use this memcpy routine with the 'prepare for store' - * prefetch you may want to set USE_MEMMOVE_FOR_OVERLAP in order to avoid - * the problem of running memcpy on overlapping buffers. - * - * There are ifdef'ed sections of this memcpy to make sure that it does not - * do prefetches on cache lines that are not going to be completely written. - * This code is only needed and only used when PREFETCH_STORE_HINT is set to - * PREFETCH_HINT_PREPAREFORSTORE. This code assumes that cache lines are - * 32 bytes and if the cache line is larger it will not work correctly. - */ - -#ifdef USE_PREFETCH -# define PREFETCH_HINT_LOAD 0 -# define PREFETCH_HINT_STORE 1 -# define PREFETCH_HINT_LOAD_STREAMED 4 -# define PREFETCH_HINT_STORE_STREAMED 5 -# define PREFETCH_HINT_LOAD_RETAINED 6 -# define PREFETCH_HINT_STORE_RETAINED 7 -# define PREFETCH_HINT_WRITEBACK_INVAL 25 -# define PREFETCH_HINT_PREPAREFORSTORE 30 - -/* - * If we have not picked out what hints to use at this point use the - * standard load and store prefetch hints. - */ -# ifndef PREFETCH_STORE_HINT -# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE -# endif -# ifndef PREFETCH_LOAD_HINT -# define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD -# endif - -/* - * We double everything when USE_DOUBLE is true so we do 2 prefetches to - * get 64 bytes in that case. The assumption is that each individual - * prefetch brings in 32 bytes. - */ - -# ifdef USE_DOUBLE -# define PREFETCH_CHUNK 64 -# define PREFETCH_FOR_LOAD(chunk, reg) \ - pref PREFETCH_LOAD_HINT, (chunk)*64(reg); \ - pref PREFETCH_LOAD_HINT, ((chunk)*64)+32(reg) -# define PREFETCH_FOR_STORE(chunk, reg) \ - pref PREFETCH_STORE_HINT, (chunk)*64(reg); \ - pref PREFETCH_STORE_HINT, ((chunk)*64)+32(reg) -# else -# define PREFETCH_CHUNK 32 -# define PREFETCH_FOR_LOAD(chunk, reg) \ - pref PREFETCH_LOAD_HINT, (chunk)*32(reg) -# define PREFETCH_FOR_STORE(chunk, reg) \ - pref PREFETCH_STORE_HINT, (chunk)*32(reg) -# endif -/* MAX_PREFETCH_SIZE is the maximum size of a prefetch, it must not be less - * than PREFETCH_CHUNK, the assumed size of each prefetch. If the real size - * of a prefetch is greater than MAX_PREFETCH_SIZE and the PREPAREFORSTORE - * hint is used, the code will not work correctly. If PREPAREFORSTORE is not - * used then MAX_PREFETCH_SIZE does not matter. */ -# define MAX_PREFETCH_SIZE 128 -/* PREFETCH_LIMIT is set based on the fact that we never use an offset greater - * than 5 on a STORE prefetch and that a single prefetch can never be larger - * than MAX_PREFETCH_SIZE. We add the extra 32 when USE_DOUBLE is set because - * we actually do two prefetches in that case, one 32 bytes after the other. */ -# ifdef USE_DOUBLE -# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + 32 + MAX_PREFETCH_SIZE -# else -# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + MAX_PREFETCH_SIZE -# endif -# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) \ - && ((PREFETCH_CHUNK * 4) < MAX_PREFETCH_SIZE) -/* We cannot handle this because the initial prefetches may fetch bytes that - * are before the buffer being copied. We start copies with an offset - * of 4 so avoid this situation when using PREPAREFORSTORE. */ -#error "PREFETCH_CHUNK is too large and/or MAX_PREFETCH_SIZE is too small." -# endif -#else /* USE_PREFETCH not defined */ -# define PREFETCH_FOR_LOAD(offset, reg) -# define PREFETCH_FOR_STORE(offset, reg) -#endif - -#if __mips_isa_rev > 5 -# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) -# undef PREFETCH_STORE_HINT -# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE_STREAMED -# endif -# define R6_CODE -#endif - -/* Allow the routine to be named something else if desired. */ -#ifndef MEMCPY_NAME -# define MEMCPY_NAME memcpy -#endif - -/* We use these 32/64 bit registers as temporaries to do the copying. */ -#define REG0 t0 -#define REG1 t1 -#define REG2 t2 -#define REG3 t3 -#if defined(_MIPS_SIM) && ((_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABIO64)) -# define REG4 t4 -# define REG5 t5 -# define REG6 t6 -# define REG7 t7 -#else -# define REG4 ta0 -# define REG5 ta1 -# define REG6 ta2 -# define REG7 ta3 -#endif - -/* We load/store 64 bits at a time when USE_DOUBLE is true. - * The C_ prefix stands for CHUNK and is used to avoid macro name - * conflicts with system header files. */ - -#ifdef USE_DOUBLE -# define C_ST sd -# define C_LD ld -# ifdef __MIPSEB -# define C_LDHI ldl /* high part is left in big-endian */ -# define C_STHI sdl /* high part is left in big-endian */ -# define C_LDLO ldr /* low part is right in big-endian */ -# define C_STLO sdr /* low part is right in big-endian */ -# else -# define C_LDHI ldr /* high part is right in little-endian */ -# define C_STHI sdr /* high part is right in little-endian */ -# define C_LDLO ldl /* low part is left in little-endian */ -# define C_STLO sdl /* low part is left in little-endian */ -# endif -# define C_ALIGN dalign /* r6 align instruction */ -#else -# define C_ST sw -# define C_LD lw -# ifdef __MIPSEB -# define C_LDHI lwl /* high part is left in big-endian */ -# define C_STHI swl /* high part is left in big-endian */ -# define C_LDLO lwr /* low part is right in big-endian */ -# define C_STLO swr /* low part is right in big-endian */ -# else -# define C_LDHI lwr /* high part is right in little-endian */ -# define C_STHI swr /* high part is right in little-endian */ -# define C_LDLO lwl /* low part is left in little-endian */ -# define C_STLO swl /* low part is left in little-endian */ -# endif -# define C_ALIGN align /* r6 align instruction */ -#endif - -/* Bookkeeping values for 32 vs. 64 bit mode. */ -#ifdef USE_DOUBLE -# define NSIZE 8 -# define NSIZEMASK 0x3f -# define NSIZEDMASK 0x7f -#else -# define NSIZE 4 -# define NSIZEMASK 0x1f -# define NSIZEDMASK 0x3f -#endif -#define UNIT(unit) ((unit)*NSIZE) -#define UNITM1(unit) (((unit)*NSIZE)-1) - -#ifdef ANDROID_CHANGES -LEAF(MEMCPY_NAME, 0) -#else -LEAF(MEMCPY_NAME) -#endif - .set nomips16 -/* - * Below we handle the case where memcpy is called with overlapping src and dst. - * Although memcpy is not required to handle this case, some parts of Android - * like Skia rely on such usage. We call memmove to handle such cases. - */ -#ifdef USE_MEMMOVE_FOR_OVERLAP - PTR_SUBU t0,a0,a1 - PTR_SRA t2,t0,31 - xor t1,t0,t2 - PTR_SUBU t0,t1,t2 - sltu t2,t0,a2 - la t9,memmove - beq t2,zero,L(memcpy) - jr t9 -L(memcpy): -#endif -/* - * If the size is less than 2*NSIZE (8 or 16), go to L(lastb). Regardless of - * size, copy dst pointer to v0 for the return value. - */ - slti t2,a2,(2 * NSIZE) -#if defined(RETURN_FIRST_PREFETCH) || defined(RETURN_LAST_PREFETCH) - move v0,zero -#else - move v0,a0 -#endif - bne t2,zero,L(lasts) - -#ifndef R6_CODE - -/* - * If src and dst have different alignments, go to L(unaligned), if they - * have the same alignment (but are not actually aligned) do a partial - * load/store to make them aligned. If they are both already aligned - * we can start copying at L(aligned). - */ - xor t8,a1,a0 - andi t8,t8,(NSIZE-1) /* t8 is a0/a1 word-displacement */ - PTR_SUBU a3, zero, a0 - bne t8,zero,L(unaligned) - - andi a3,a3,(NSIZE-1) /* copy a3 bytes to align a0/a1 */ - PTR_SUBU a2,a2,a3 /* a2 is the remining bytes count */ - beq a3,zero,L(aligned) /* if a3=0, it is already aligned */ - - C_LDHI t8,0(a1) - PTR_ADDU a1,a1,a3 - C_STHI t8,0(a0) - PTR_ADDU a0,a0,a3 - -#else /* R6_CODE */ - -/* - * Align the destination and hope that the source gets aligned too. If it - * doesn't we jump to L(r6_unaligned*) to do unaligned copies using the r6 - * align instruction. - */ - andi t8,a0,7 -#ifdef __mips_micromips - auipc t9,%pcrel_hi(L(atable)) - addiu t9,t9,%pcrel_lo(L(atable)+4) - PTR_LSA t9,t8,t9,1 -#else - lapc t9,L(atable) - PTR_LSA t9,t8,t9,2 -#endif - jrc t9 -L(atable): - PTR_BC L(lb0) - PTR_BC L(lb7) - PTR_BC L(lb6) - PTR_BC L(lb5) - PTR_BC L(lb4) - PTR_BC L(lb3) - PTR_BC L(lb2) - PTR_BC L(lb1) -L(lb7): - lb a3, 6(a1) - sb a3, 6(a0) -L(lb6): - lb a3, 5(a1) - sb a3, 5(a0) -L(lb5): - lb a3, 4(a1) - sb a3, 4(a0) -L(lb4): - lb a3, 3(a1) - sb a3, 3(a0) -L(lb3): - lb a3, 2(a1) - sb a3, 2(a0) -L(lb2): - lb a3, 1(a1) - sb a3, 1(a0) -L(lb1): - lb a3, 0(a1) - sb a3, 0(a0) - - li t9,8 - subu t8,t9,t8 - PTR_SUBU a2,a2,t8 - PTR_ADDU a0,a0,t8 - PTR_ADDU a1,a1,t8 -L(lb0): - - andi t8,a1,(NSIZE-1) -#ifdef __mips_micromips - auipc t9,%pcrel_hi(L(jtable)) - addiu t9,t9,%pcrel_lo(L(jtable)+4) - PTR_LSA t9,t8,t9,1 -#else - lapc t9,L(jtable) - PTR_LSA t9,t8,t9,2 -#endif - jrc t9 -L(jtable): - PTR_BC L(aligned) - PTR_BC L(r6_unaligned1) - PTR_BC L(r6_unaligned2) - PTR_BC L(r6_unaligned3) -#ifdef USE_DOUBLE - PTR_BC L(r6_unaligned4) - PTR_BC L(r6_unaligned5) - PTR_BC L(r6_unaligned6) - PTR_BC L(r6_unaligned7) -#endif -#endif /* R6_CODE */ - -L(aligned): - -/* - * Now dst/src are both aligned to (word or double word) aligned addresses - * Set a2 to count how many bytes we have to copy after all the 64/128 byte - * chunks are copied and a3 to the dst pointer after all the 64/128 byte - * chunks have been copied. We will loop, incrementing a0 and a1 until a0 - * equals a3. - */ - - andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */ - PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */ - beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */ - PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */ - -/* When in the loop we may prefetch with the 'prepare to store' hint, - * in this case the a0+x should not be past the "t0-32" address. This - * means: for x=128 the last "safe" a0 address is "t0-160". Alternatively, - * for x=64 the last "safe" a0 address is "t0-96" In the current version we - * will use "prefetch hint,128(a0)", so "t0-160" is the limit. - */ -#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) - PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */ - PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */ -#endif - PREFETCH_FOR_LOAD (0, a1) - PREFETCH_FOR_LOAD (1, a1) - PREFETCH_FOR_LOAD (2, a1) - PREFETCH_FOR_LOAD (3, a1) -#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE) - PREFETCH_FOR_STORE (1, a0) - PREFETCH_FOR_STORE (2, a0) - PREFETCH_FOR_STORE (3, a0) -#endif -#if defined(RETURN_FIRST_PREFETCH) && defined(USE_PREFETCH) -# if PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE - sltu v1,t9,a0 - bgtz v1,L(skip_set) - PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4) -L(skip_set): -# else - PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1) -# endif -#endif -#if defined(RETURN_LAST_PREFETCH) && defined(USE_PREFETCH) \ - && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE) - PTR_ADDIU v0,a0,(PREFETCH_CHUNK*3) -# ifdef USE_DOUBLE - PTR_ADDIU v0,v0,32 -# endif -#endif -L(loop16w): - C_LD t0,UNIT(0)(a1) -/* We need to separate out the C_LD instruction here so that it will work - both when it is used by itself and when it is used with the branch - instruction. */ -#if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) - sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */ - C_LD t1,UNIT(1)(a1) - bgtz v1,L(skip_pref) -#else - C_LD t1,UNIT(1)(a1) -#endif -#ifdef R6_CODE - PREFETCH_FOR_STORE (2, a0) -#else - PREFETCH_FOR_STORE (4, a0) - PREFETCH_FOR_STORE (5, a0) -#endif -#if defined(RETURN_LAST_PREFETCH) && defined(USE_PREFETCH) - PTR_ADDIU v0,a0,(PREFETCH_CHUNK*5) -# ifdef USE_DOUBLE - PTR_ADDIU v0,v0,32 -# endif -#endif -L(skip_pref): - C_LD REG2,UNIT(2)(a1) - C_LD REG3,UNIT(3)(a1) - C_LD REG4,UNIT(4)(a1) - C_LD REG5,UNIT(5)(a1) - C_LD REG6,UNIT(6)(a1) - C_LD REG7,UNIT(7)(a1) -#ifdef R6_CODE - PREFETCH_FOR_LOAD (3, a1) -#else - PREFETCH_FOR_LOAD (4, a1) -#endif - C_ST t0,UNIT(0)(a0) - C_ST t1,UNIT(1)(a0) - C_ST REG2,UNIT(2)(a0) - C_ST REG3,UNIT(3)(a0) - C_ST REG4,UNIT(4)(a0) - C_ST REG5,UNIT(5)(a0) - C_ST REG6,UNIT(6)(a0) - C_ST REG7,UNIT(7)(a0) - - C_LD t0,UNIT(8)(a1) - C_LD t1,UNIT(9)(a1) - C_LD REG2,UNIT(10)(a1) - C_LD REG3,UNIT(11)(a1) - C_LD REG4,UNIT(12)(a1) - C_LD REG5,UNIT(13)(a1) - C_LD REG6,UNIT(14)(a1) - C_LD REG7,UNIT(15)(a1) -#ifndef R6_CODE - PREFETCH_FOR_LOAD (5, a1) -#endif - C_ST t0,UNIT(8)(a0) - C_ST t1,UNIT(9)(a0) - C_ST REG2,UNIT(10)(a0) - C_ST REG3,UNIT(11)(a0) - C_ST REG4,UNIT(12)(a0) - C_ST REG5,UNIT(13)(a0) - C_ST REG6,UNIT(14)(a0) - C_ST REG7,UNIT(15)(a0) - PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */ - PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */ - bne a0,a3,L(loop16w) - move a2,t8 - -/* Here we have src and dest word-aligned but less than 64-bytes or - * 128 bytes to go. Check for a 32(64) byte chunk and copy if there - * is one. Otherwise jump down to L(chk1w) to handle the tail end of - * the copy. - */ - -L(chkw): - PREFETCH_FOR_LOAD (0, a1) - andi t8,a2,NSIZEMASK /* Is there a 32-byte/64-byte chunk. */ - /* The t8 is the reminder count past 32-bytes */ - beq a2,t8,L(chk1w) /* When a2=t8, no 32-byte chunk */ - C_LD t0,UNIT(0)(a1) - C_LD t1,UNIT(1)(a1) - C_LD REG2,UNIT(2)(a1) - C_LD REG3,UNIT(3)(a1) - C_LD REG4,UNIT(4)(a1) - C_LD REG5,UNIT(5)(a1) - C_LD REG6,UNIT(6)(a1) - C_LD REG7,UNIT(7)(a1) - PTR_ADDIU a1,a1,UNIT(8) - C_ST t0,UNIT(0)(a0) - C_ST t1,UNIT(1)(a0) - C_ST REG2,UNIT(2)(a0) - C_ST REG3,UNIT(3)(a0) - C_ST REG4,UNIT(4)(a0) - C_ST REG5,UNIT(5)(a0) - C_ST REG6,UNIT(6)(a0) - C_ST REG7,UNIT(7)(a0) - PTR_ADDIU a0,a0,UNIT(8) - -/* - * Here we have less than 32(64) bytes to copy. Set up for a loop to - * copy one word (or double word) at a time. Set a2 to count how many - * bytes we have to copy after all the word (or double word) chunks are - * copied and a3 to the dst pointer after all the (d)word chunks have - * been copied. We will loop, incrementing a0 and a1 until a0 equals a3. - */ -L(chk1w): - andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */ - PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */ - beq a2,t8,L(lastw) - PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */ - -/* copying in words (4-byte or 8-byte chunks) */ -L(wordCopy_loop): - C_LD REG3,UNIT(0)(a1) - PTR_ADDIU a0,a0,UNIT(1) - PTR_ADDIU a1,a1,UNIT(1) - C_ST REG3,UNIT(-1)(a0) - bne a0,a3,L(wordCopy_loop) - -/* If we have been copying double words, see if we can copy a single word - before doing byte copies. We can have, at most, one word to copy. */ - -L(lastw): -#ifdef USE_DOUBLE - andi t8,a2,3 /* a2 is the remainder past 4 byte chunks. */ - beq t8,a2,L(lastb) - move a2,t8 - lw REG3,0(a1) - sw REG3,0(a0) - PTR_ADDIU a0,a0,4 - PTR_ADDIU a1,a1,4 -#endif - -/* Copy the last 8 (or 16) bytes */ -L(lastb): - PTR_ADDU a3,a0,a2 /* a3 is the last dst address */ - blez a2,L(leave) -L(lastbloop): - lb v1,0(a1) - PTR_ADDIU a0,a0,1 - PTR_ADDIU a1,a1,1 - sb v1,-1(a0) - bne a0,a3,L(lastbloop) -L(leave): - jr ra - -/* We jump here with a memcpy of less than 8 or 16 bytes, depending on - whether or not USE_DOUBLE is defined. Instead of just doing byte - copies, check the alignment and size and use lw/sw if possible. - Otherwise, do byte copies. */ - -L(lasts): - andi t8,a2,3 - beq t8,a2,L(lastb) - - andi t9,a0,3 - bne t9,zero,L(lastb) - andi t9,a1,3 - bne t9,zero,L(lastb) - - PTR_SUBU a3,a2,t8 - PTR_ADDU a3,a0,a3 - -L(wcopy_loop): - lw REG3,0(a1) - PTR_ADDIU a0,a0,4 - PTR_ADDIU a1,a1,4 - bne a0,a3,L(wcopy_loop) - sw REG3,-4(a0) - - b L(lastb) - move a2,t8 - -#ifndef R6_CODE -/* - * UNALIGNED case, got here with a3 = "negu a0" - * This code is nearly identical to the aligned code above - * but only the destination (not the source) gets aligned - * so we need to do partial loads of the source followed - * by normal stores to the destination (once we have aligned - * the destination). - */ - -L(unaligned): - andi a3,a3,(NSIZE-1) /* copy a3 bytes to align a0/a1 */ - PTR_SUBU a2,a2,a3 /* a2 is the remining bytes count */ - beqz a3,L(ua_chk16w) /* if a3=0, it is already aligned */ - - C_LDHI v1,UNIT(0)(a1) - C_LDLO v1,UNITM1(1)(a1) - PTR_ADDU a1,a1,a3 - C_STHI v1,UNIT(0)(a0) - PTR_ADDU a0,a0,a3 - -/* - * Now the destination (but not the source) is aligned - * Set a2 to count how many bytes we have to copy after all the 64/128 byte - * chunks are copied and a3 to the dst pointer after all the 64/128 byte - * chunks have been copied. We will loop, incrementing a0 and a1 until a0 - * equals a3. - */ - -L(ua_chk16w): - andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */ - PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */ - beq a2,t8,L(ua_chkw) /* if a2==t8, no 64-byte/128-byte chunks */ - PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */ - -# if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) - PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */ - PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */ -# endif - PREFETCH_FOR_LOAD (0, a1) - PREFETCH_FOR_LOAD (1, a1) - PREFETCH_FOR_LOAD (2, a1) -# if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE) - PREFETCH_FOR_STORE (1, a0) - PREFETCH_FOR_STORE (2, a0) - PREFETCH_FOR_STORE (3, a0) -# endif -# if defined(RETURN_FIRST_PREFETCH) && defined(USE_PREFETCH) -# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) - sltu v1,t9,a0 - bgtz v1,L(ua_skip_set) - PTR_ADDIU v0,a0,(PREFETCH_CHUNK*4) -L(ua_skip_set): -# else - PTR_ADDIU v0,a0,(PREFETCH_CHUNK*1) -# endif -# endif -L(ua_loop16w): - PREFETCH_FOR_LOAD (3, a1) - C_LDHI t0,UNIT(0)(a1) - C_LDHI t1,UNIT(1)(a1) - C_LDHI REG2,UNIT(2)(a1) -/* We need to separate out the C_LDHI instruction here so that it will work - both when it is used by itself and when it is used with the branch - instruction. */ -# if defined(USE_PREFETCH) && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) - sltu v1,t9,a0 - C_LDHI REG3,UNIT(3)(a1) - bgtz v1,L(ua_skip_pref) -# else - C_LDHI REG3,UNIT(3)(a1) -# endif - PREFETCH_FOR_STORE (4, a0) - PREFETCH_FOR_STORE (5, a0) -L(ua_skip_pref): - C_LDHI REG4,UNIT(4)(a1) - C_LDHI REG5,UNIT(5)(a1) - C_LDHI REG6,UNIT(6)(a1) - C_LDHI REG7,UNIT(7)(a1) - C_LDLO t0,UNITM1(1)(a1) - C_LDLO t1,UNITM1(2)(a1) - C_LDLO REG2,UNITM1(3)(a1) - C_LDLO REG3,UNITM1(4)(a1) - C_LDLO REG4,UNITM1(5)(a1) - C_LDLO REG5,UNITM1(6)(a1) - C_LDLO REG6,UNITM1(7)(a1) - C_LDLO REG7,UNITM1(8)(a1) - PREFETCH_FOR_LOAD (4, a1) - C_ST t0,UNIT(0)(a0) - C_ST t1,UNIT(1)(a0) - C_ST REG2,UNIT(2)(a0) - C_ST REG3,UNIT(3)(a0) - C_ST REG4,UNIT(4)(a0) - C_ST REG5,UNIT(5)(a0) - C_ST REG6,UNIT(6)(a0) - C_ST REG7,UNIT(7)(a0) - C_LDHI t0,UNIT(8)(a1) - C_LDHI t1,UNIT(9)(a1) - C_LDHI REG2,UNIT(10)(a1) - C_LDHI REG3,UNIT(11)(a1) - C_LDHI REG4,UNIT(12)(a1) - C_LDHI REG5,UNIT(13)(a1) - C_LDHI REG6,UNIT(14)(a1) - C_LDHI REG7,UNIT(15)(a1) - C_LDLO t0,UNITM1(9)(a1) - C_LDLO t1,UNITM1(10)(a1) - C_LDLO REG2,UNITM1(11)(a1) - C_LDLO REG3,UNITM1(12)(a1) - C_LDLO REG4,UNITM1(13)(a1) - C_LDLO REG5,UNITM1(14)(a1) - C_LDLO REG6,UNITM1(15)(a1) - C_LDLO REG7,UNITM1(16)(a1) - PREFETCH_FOR_LOAD (5, a1) - C_ST t0,UNIT(8)(a0) - C_ST t1,UNIT(9)(a0) - C_ST REG2,UNIT(10)(a0) - C_ST REG3,UNIT(11)(a0) - C_ST REG4,UNIT(12)(a0) - C_ST REG5,UNIT(13)(a0) - C_ST REG6,UNIT(14)(a0) - C_ST REG7,UNIT(15)(a0) - PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */ - PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */ - bne a0,a3,L(ua_loop16w) - move a2,t8 - -/* Here we have src and dest word-aligned but less than 64-bytes or - * 128 bytes to go. Check for a 32(64) byte chunk and copy if there - * is one. Otherwise jump down to L(ua_chk1w) to handle the tail end of - * the copy. */ - -L(ua_chkw): - PREFETCH_FOR_LOAD (0, a1) - andi t8,a2,NSIZEMASK /* Is there a 32-byte/64-byte chunk. */ - /* t8 is the reminder count past 32-bytes */ - beq a2,t8,L(ua_chk1w) /* When a2=t8, no 32-byte chunk */ - C_LDHI t0,UNIT(0)(a1) - C_LDHI t1,UNIT(1)(a1) - C_LDHI REG2,UNIT(2)(a1) - C_LDHI REG3,UNIT(3)(a1) - C_LDHI REG4,UNIT(4)(a1) - C_LDHI REG5,UNIT(5)(a1) - C_LDHI REG6,UNIT(6)(a1) - C_LDHI REG7,UNIT(7)(a1) - C_LDLO t0,UNITM1(1)(a1) - C_LDLO t1,UNITM1(2)(a1) - C_LDLO REG2,UNITM1(3)(a1) - C_LDLO REG3,UNITM1(4)(a1) - C_LDLO REG4,UNITM1(5)(a1) - C_LDLO REG5,UNITM1(6)(a1) - C_LDLO REG6,UNITM1(7)(a1) - C_LDLO REG7,UNITM1(8)(a1) - PTR_ADDIU a1,a1,UNIT(8) - C_ST t0,UNIT(0)(a0) - C_ST t1,UNIT(1)(a0) - C_ST REG2,UNIT(2)(a0) - C_ST REG3,UNIT(3)(a0) - C_ST REG4,UNIT(4)(a0) - C_ST REG5,UNIT(5)(a0) - C_ST REG6,UNIT(6)(a0) - C_ST REG7,UNIT(7)(a0) - PTR_ADDIU a0,a0,UNIT(8) -/* - * Here we have less than 32(64) bytes to copy. Set up for a loop to - * copy one word (or double word) at a time. - */ -L(ua_chk1w): - andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */ - PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */ - beq a2,t8,L(ua_smallCopy) - PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */ - -/* copying in words (4-byte or 8-byte chunks) */ -L(ua_wordCopy_loop): - C_LDHI v1,UNIT(0)(a1) - C_LDLO v1,UNITM1(1)(a1) - PTR_ADDIU a0,a0,UNIT(1) - PTR_ADDIU a1,a1,UNIT(1) - C_ST v1,UNIT(-1)(a0) - bne a0,a3,L(ua_wordCopy_loop) - -/* Copy the last 8 (or 16) bytes */ -L(ua_smallCopy): - PTR_ADDU a3,a0,a2 /* a3 is the last dst address */ - beqz a2,L(leave) -L(ua_smallCopy_loop): - lb v1,0(a1) - PTR_ADDIU a0,a0,1 - PTR_ADDIU a1,a1,1 - sb v1,-1(a0) - bne a0,a3,L(ua_smallCopy_loop) - - jr ra - -#else /* R6_CODE */ - -# ifdef __MIPSEB -# define SWAP_REGS(X,Y) X, Y -# define ALIGN_OFFSET(N) (N) -# else -# define SWAP_REGS(X,Y) Y, X -# define ALIGN_OFFSET(N) (NSIZE-N) -# endif -# define R6_UNALIGNED_WORD_COPY(BYTEOFFSET) \ - andi REG7, a2, (NSIZE-1);/* REG7 is # of bytes to by bytes. */ \ - PTR_SUBU a3, a2, REG7; /* a3 is number of bytes to be copied in */ \ - /* (d)word chunks. */ \ - beq REG7, a2, L(lastb); /* Check for bytes to copy by word */ \ - move a2, REG7; /* a2 is # of bytes to copy byte by byte */ \ - /* after word loop is finished. */ \ - PTR_ADDU REG6, a0, a3; /* REG6 is the dst address after loop. */ \ - PTR_SUBU REG2, a1, t8; /* REG2 is the aligned src address. */ \ - PTR_ADDU a1, a1, a3; /* a1 is addr of source after word loop. */ \ - C_LD t0, UNIT(0)(REG2); /* Load first part of source. */ \ -L(r6_ua_wordcopy##BYTEOFFSET): \ - C_LD t1, UNIT(1)(REG2); /* Load second part of source. */ \ - C_ALIGN REG3, SWAP_REGS(t1,t0), ALIGN_OFFSET(BYTEOFFSET); \ - PTR_ADDIU a0, a0, UNIT(1); /* Increment destination pointer. */ \ - PTR_ADDIU REG2, REG2, UNIT(1); /* Increment aligned source pointer.*/ \ - move t0, t1; /* Move second part of source to first. */ \ - C_ST REG3, UNIT(-1)(a0); \ - bne a0, REG6,L(r6_ua_wordcopy##BYTEOFFSET); \ - j L(lastb); \ - - /* We are generating R6 code, the destination is 4 byte aligned and - the source is not 4 byte aligned. t8 is 1, 2, or 3 depending on the - alignment of the source. */ - -L(r6_unaligned1): - R6_UNALIGNED_WORD_COPY(1) -L(r6_unaligned2): - R6_UNALIGNED_WORD_COPY(2) -L(r6_unaligned3): - R6_UNALIGNED_WORD_COPY(3) -# ifdef USE_DOUBLE -L(r6_unaligned4): - R6_UNALIGNED_WORD_COPY(4) -L(r6_unaligned5): - R6_UNALIGNED_WORD_COPY(5) -L(r6_unaligned6): - R6_UNALIGNED_WORD_COPY(6) -L(r6_unaligned7): - R6_UNALIGNED_WORD_COPY(7) -# endif -#endif /* R6_CODE */ - - .set at -END(MEMCPY_NAME) -#ifndef ANDROID_CHANGES -# ifdef _LIBC -libc_hidden_builtin_def (MEMCPY_NAME) -# endif -#endif diff --git a/sysdeps/mips/memcpy.c b/sysdeps/mips/memcpy.c new file mode 100644 index 0000000000..8c3aec7b36 --- /dev/null +++ b/sysdeps/mips/memcpy.c @@ -0,0 +1,415 @@ +/* + * Copyright (C) 2024 MIPS Tech, LLC + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifdef __GNUC__ + +#undef memcpy + +/* Typical observed latency in cycles in fetching from DRAM. */ +#define LATENCY_CYCLES 63 + +/* Pre-fetch performance is subject to accurate prefetch ahead, + which in turn depends on both the cache-line size and the amount + of look-ahead. Since cache-line size is not nominally fixed in + a typically library built for multiple platforms, we make conservative + assumptions in the default case. This code will typically operate + on such conservative assumptions, but if compiled with the correct + -mtune=xx options, will perform even better on those specific + platforms. */ +#if defined(_MIPS_TUNE_OCTEON2) || defined(_MIPS_TUNE_OCTEON3) + #define CACHE_LINE 128 + #define BLOCK_CYCLES 30 + #undef LATENCY_CYCLES + #define LATENCY_CYCLES 150 +#elif defined(_MIPS_TUNE_I6400) || defined(_MIPS_TUNE_I6500) + #define CACHE_LINE 64 + #define BLOCK_CYCLES 16 +#elif defined(_MIPS_TUNE_P6600) + #define CACHE_LINE 32 + #define BLOCK_CYCLES 12 +#elif defined(_MIPS_TUNE_INTERAPTIV) || defined(_MIPS_TUNE_INTERAPTIV_MR2) + #define CACHE_LINE 32 + #define BLOCK_CYCLES 30 +#else + #define CACHE_LINE 32 + #define BLOCK_CYCLES 11 +#endif + +/* Pre-fetch look ahead = ceil (latency / block-cycles) */ +#define PREF_AHEAD (LATENCY_CYCLES / BLOCK_CYCLES \ + + ((LATENCY_CYCLES % BLOCK_CYCLES) == 0 ? 0 : 1)) + +/* Unroll-factor, controls how many words at a time in the core loop. */ +#define BLOCK (CACHE_LINE == 128 ? 16 : 8) + +#define __overloadable +#if !defined(UNALIGNED_INSTR_SUPPORT) +/* does target have unaligned lw/ld/ualw/uald instructions? */ + #define UNALIGNED_INSTR_SUPPORT 0 +#if (__mips_isa_rev < 6 && !defined(__mips1)) + #undef UNALIGNED_INSTR_SUPPORT + #define UNALIGNED_INSTR_SUPPORT 1 + #endif +#endif +#if !defined(HW_UNALIGNED_SUPPORT) +/* Does target have hardware support for unaligned accesses? */ + #define HW_UNALIGNED_SUPPORT 0 + #if __mips_isa_rev >= 6 + #undef HW_UNALIGNED_SUPPORT + #define HW_UNALIGNED_SUPPORT 1 + #endif +#endif +#define ENABLE_PREFETCH 1 +#if ENABLE_PREFETCH + #define PREFETCH(addr) __builtin_prefetch (addr, 0, 0) +#else + #define PREFETCH(addr) +#endif + +#include + +#ifdef __mips64 +typedef unsigned long long reg_t; +typedef struct +{ + reg_t B0:8, B1:8, B2:8, B3:8, B4:8, B5:8, B6:8, B7:8; +} bits_t; +#else +typedef unsigned long reg_t; +typedef struct +{ + reg_t B0:8, B1:8, B2:8, B3:8; +} bits_t; +#endif + +#define CACHE_LINES_PER_BLOCK ((BLOCK * sizeof (reg_t) > CACHE_LINE) ? \ + (BLOCK * sizeof (reg_t) / CACHE_LINE) \ + : 1) + +typedef union +{ + reg_t v; + bits_t b; +} bitfields_t; + +#define DO_BYTE(a, i) \ + a[i] = bw.b.B##i; \ + len--; \ + if(!len) return ret; \ + +/* This code is called when aligning a pointer, there are remaining bytes + after doing word compares, or architecture does not have some form + of unaligned support. */ +static inline void * __attribute__ ((always_inline)) +do_bytes (void *a, const void *b, unsigned long len, void *ret) +{ + unsigned char *x = (unsigned char *) a; + unsigned char *y = (unsigned char *) b; + unsigned long i; + /* 'len' might be zero here, so preloading the first two values + before the loop may access unallocated memory. */ + for (i = 0; i < len; i++) + { + *x = *y; + x++; + y++; + } + return ret; +} + +/* This code is called to copy only remaining bytes within word or doubleword */ +static inline void * __attribute__ ((always_inline)) +do_bytes_remaining (void *a, const void *b, unsigned long len, void *ret) +{ + unsigned char *x = (unsigned char *) a; + bitfields_t bw; + if(len > 0) + { + bw.v = *(reg_t *)b; + DO_BYTE(x, 0); + DO_BYTE(x, 1); + DO_BYTE(x, 2); +#ifdef __mips64 + DO_BYTE(x, 3); + DO_BYTE(x, 4); + DO_BYTE(x, 5); + DO_BYTE(x, 6); +#endif + } + return ret; +} + +static inline void * __attribute__ ((always_inline)) +do_words_remaining (reg_t *a, const reg_t *b, unsigned long words, + unsigned long bytes, void *ret) +{ + /* Use a set-back so that load/stores have incremented addresses in + order to promote bonding. */ + int off = (BLOCK - words); + a -= off; + b -= off; + switch (off) + { + case 1: a[1] = b[1]; // Fall through + case 2: a[2] = b[2]; // Fall through + case 3: a[3] = b[3]; // Fall through + case 4: a[4] = b[4]; // Fall through + case 5: a[5] = b[5]; // Fall through + case 6: a[6] = b[6]; // Fall through + case 7: a[7] = b[7]; // Fall through +#if BLOCK==16 + case 8: a[8] = b[8]; // Fall through + case 9: a[9] = b[9]; // Fall through + case 10: a[10] = b[10]; // Fall through + case 11: a[11] = b[11]; // Fall through + case 12: a[12] = b[12]; // Fall through + case 13: a[13] = b[13]; // Fall through + case 14: a[14] = b[14]; // Fall through + case 15: a[15] = b[15]; +#endif + } + return do_bytes_remaining (a + BLOCK, b + BLOCK, bytes, ret); +} + +#if !HW_UNALIGNED_SUPPORT +#if UNALIGNED_INSTR_SUPPORT +/* For MIPS GCC, there are no unaligned builtins - so this struct forces + the compiler to treat the pointer access as unaligned. */ +struct ulw +{ + reg_t uli; +} __attribute__ ((packed)); +static inline void * __attribute__ ((always_inline)) +do_uwords_remaining (struct ulw *a, const reg_t *b, unsigned long words, + unsigned long bytes, void *ret) +{ + /* Use a set-back so that load/stores have incremented addresses in + order to promote bonding. */ + int off = (BLOCK - words); + a -= off; + b -= off; + switch (off) + { + case 1: a[1].uli = b[1]; // Fall through + case 2: a[2].uli = b[2]; // Fall through + case 3: a[3].uli = b[3]; // Fall through + case 4: a[4].uli = b[4]; // Fall through + case 5: a[5].uli = b[5]; // Fall through + case 6: a[6].uli = b[6]; // Fall through + case 7: a[7].uli = b[7]; // Fall through +#if BLOCK==16 + case 8: a[8].uli = b[8]; // Fall through + case 9: a[9].uli = b[9]; // Fall through + case 10: a[10].uli = b[10]; // Fall through + case 11: a[11].uli = b[11]; // Fall through + case 12: a[12].uli = b[12]; // Fall through + case 13: a[13].uli = b[13]; // Fall through + case 14: a[14].uli = b[14]; // Fall through + case 15: a[15].uli = b[15]; +#endif + } + return do_bytes_remaining (a + BLOCK, b + BLOCK, bytes, ret); +} + +/* The first pointer is not aligned while second pointer is. */ +static void * +unaligned_words (struct ulw *a, const reg_t * b, + unsigned long words, unsigned long bytes, void *ret) +{ + unsigned long i, words_by_block, words_by_1; + words_by_1 = words % BLOCK; + words_by_block = words / BLOCK; + for (; words_by_block > 0; words_by_block--) + { + if (words_by_block >= PREF_AHEAD - CACHE_LINES_PER_BLOCK) + for (i = 0; i < CACHE_LINES_PER_BLOCK; i++) + PREFETCH (b + (BLOCK / CACHE_LINES_PER_BLOCK) * (PREF_AHEAD + i)); + + reg_t y0 = b[0], y1 = b[1], y2 = b[2], y3 = b[3]; + reg_t y4 = b[4], y5 = b[5], y6 = b[6], y7 = b[7]; + a[0].uli = y0; + a[1].uli = y1; + a[2].uli = y2; + a[3].uli = y3; + a[4].uli = y4; + a[5].uli = y5; + a[6].uli = y6; + a[7].uli = y7; +#if BLOCK==16 + y0 = b[8], y1 = b[9], y2 = b[10], y3 = b[11]; + y4 = b[12], y5 = b[13], y6 = b[14], y7 = b[15]; + a[8].uli = y0; + a[9].uli = y1; + a[10].uli = y2; + a[11].uli = y3; + a[12].uli = y4; + a[13].uli = y5; + a[14].uli = y6; + a[15].uli = y7; +#endif + a += BLOCK; + b += BLOCK; + } + + /* Mop up any remaining bytes. */ + return do_uwords_remaining (a, b, words_by_1, bytes, ret); +} + +#else + +/* No HW support or unaligned lw/ld/ualw/uald instructions. */ +static void * +unaligned_words (reg_t * a, const reg_t * b, + unsigned long words, unsigned long bytes, void *ret) +{ + unsigned long i; + unsigned char *x; + for (i = 0; i < words; i++) + { + bitfields_t bw; + bw.v = *((reg_t*) b); + x = (unsigned char *) a; + x[0] = bw.b.B0; + x[1] = bw.b.B1; + x[2] = bw.b.B2; + x[3] = bw.b.B3; +#ifdef __mips64 + x[4] = bw.b.B4; + x[5] = bw.b.B5; + x[6] = bw.b.B6; + x[7] = bw.b.B7; +#endif + a += 1; + b += 1; + } + /* Mop up any remaining bytes. */ + return do_bytes_remaining (a, b, bytes, ret); +} + +#endif /* UNALIGNED_INSTR_SUPPORT */ +#endif /* HW_UNALIGNED_SUPPORT */ + +/* both pointers are aligned, or first isn't and HW support for unaligned. */ +static void * +aligned_words (reg_t * a, const reg_t * b, + unsigned long words, unsigned long bytes, void *ret) +{ + unsigned long i, words_by_block, words_by_1; + words_by_1 = words % BLOCK; + words_by_block = words / BLOCK; + for (; words_by_block > 0; words_by_block--) + { + if(words_by_block >= PREF_AHEAD - CACHE_LINES_PER_BLOCK) + for (i = 0; i < CACHE_LINES_PER_BLOCK; i++) + PREFETCH (b + ((BLOCK / CACHE_LINES_PER_BLOCK) * (PREF_AHEAD + i))); + + reg_t x0 = b[0], x1 = b[1], x2 = b[2], x3 = b[3]; + reg_t x4 = b[4], x5 = b[5], x6 = b[6], x7 = b[7]; + a[0] = x0; + a[1] = x1; + a[2] = x2; + a[3] = x3; + a[4] = x4; + a[5] = x5; + a[6] = x6; + a[7] = x7; +#if BLOCK==16 + x0 = b[8], x1 = b[9], x2 = b[10], x3 = b[11]; + x4 = b[12], x5 = b[13], x6 = b[14], x7 = b[15]; + a[8] = x0; + a[9] = x1; + a[10] = x2; + a[11] = x3; + a[12] = x4; + a[13] = x5; + a[14] = x6; + a[15] = x7; +#endif + a += BLOCK; + b += BLOCK; + } + + /* mop up any remaining bytes. */ + return do_words_remaining (a, b, words_by_1, bytes, ret); +} + +void * +memcpy (void *a, const void *b, size_t len) __overloadable +{ + unsigned long bytes, words, i; + void *ret = a; + /* shouldn't hit that often. */ + if (len <= 8) + return do_bytes (a, b, len, a); + + /* Start pre-fetches ahead of time. */ + if (len > CACHE_LINE * (PREF_AHEAD - 1)) + for (i = 1; i < PREF_AHEAD - 1; i++) + PREFETCH ((char *)b + CACHE_LINE * i); + else + for (i = 1; i < len / CACHE_LINE; i++) + PREFETCH ((char *)b + CACHE_LINE * i); + + /* Align the second pointer to word/dword alignment. + Note that the pointer is only 32-bits for o32/n32 ABIs. For + n32, loads are done as 64-bit while address remains 32-bit. */ + bytes = ((unsigned long) b) % (sizeof (reg_t)); + + if (bytes) + { + bytes = (sizeof (reg_t)) - bytes; + if (bytes > len) + bytes = len; + do_bytes (a, b, bytes, ret); + if (len == bytes) + return ret; + len -= bytes; + a = (void *) (((unsigned char *) a) + bytes); + b = (const void *) (((unsigned char *) b) + bytes); + } + + /* Second pointer now aligned. */ + words = len / sizeof (reg_t); + bytes = len % sizeof (reg_t); + +#if HW_UNALIGNED_SUPPORT + /* treat possible unaligned first pointer as aligned. */ + return aligned_words (a, b, words, bytes, ret); +#else + if (((unsigned long) a) % sizeof (reg_t) == 0) + return aligned_words (a, b, words, bytes, ret); + /* need to use unaligned instructions on first pointer. */ + return unaligned_words (a, b, words, bytes, ret); +#endif +} + +libc_hidden_builtin_def (memcpy) + +#else +#include +#endif diff --git a/sysdeps/mips/memset.S b/sysdeps/mips/memset.S deleted file mode 100644 index 833381d73f..0000000000 --- a/sysdeps/mips/memset.S +++ /dev/null @@ -1,430 +0,0 @@ -/* Copyright (C) 2013-2025 Free Software Foundation, Inc. - This file is part of the GNU C Library. - - The GNU C Library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - The GNU C Library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with the GNU C Library. If not, see - . */ - -#ifdef ANDROID_CHANGES -# include "machine/asm.h" -# include "machine/regdef.h" -# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE -#elif _LIBC -# include -# include -# include -# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE -#elif defined _COMPILING_NEWLIB -# include "machine/asm.h" -# include "machine/regdef.h" -# define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE -#else -# include -# include -#endif - -/* Check to see if the MIPS architecture we are compiling for supports - prefetching. */ - -#if (__mips == 4) || (__mips == 5) || (__mips == 32) || (__mips == 64) -# ifndef DISABLE_PREFETCH -# define USE_PREFETCH -# endif -#endif - -#if defined(_MIPS_SIM) && ((_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32)) -# ifndef DISABLE_DOUBLE -# define USE_DOUBLE -# endif -#endif - -#ifndef USE_DOUBLE -# ifndef DISABLE_DOUBLE_ALIGN -# define DOUBLE_ALIGN -# endif -#endif - - -/* Some asm.h files do not have the L macro definition. */ -#ifndef L -# if _MIPS_SIM == _ABIO32 -# define L(label) $L ## label -# else -# define L(label) .L ## label -# endif -#endif - -/* Some asm.h files do not have the PTR_ADDIU macro definition. */ -#ifndef PTR_ADDIU -# ifdef USE_DOUBLE -# define PTR_ADDIU daddiu -# else -# define PTR_ADDIU addiu -# endif -#endif - -/* New R6 instructions that may not be in asm.h. */ -#ifndef PTR_LSA -# if _MIPS_SIM == _ABI64 -# define PTR_LSA dlsa -# else -# define PTR_LSA lsa -# endif -#endif - -#if __mips_isa_rev > 5 && defined (__mips_micromips) -# define PTR_BC bc16 -#else -# define PTR_BC bc -#endif - -/* Using PREFETCH_HINT_PREPAREFORSTORE instead of PREFETCH_STORE - or PREFETCH_STORE_STREAMED offers a large performance advantage - but PREPAREFORSTORE has some special restrictions to consider. - - Prefetch with the 'prepare for store' hint does not copy a memory - location into the cache, it just allocates a cache line and zeros - it out. This means that if you do not write to the entire cache - line before writing it out to memory some data will get zero'ed out - when the cache line is written back to memory and data will be lost. - - There are ifdef'ed sections of this memcpy to make sure that it does not - do prefetches on cache lines that are not going to be completely written. - This code is only needed and only used when PREFETCH_STORE_HINT is set to - PREFETCH_HINT_PREPAREFORSTORE. This code assumes that cache lines are - less than MAX_PREFETCH_SIZE bytes and if the cache line is larger it will - not work correctly. */ - -#ifdef USE_PREFETCH -# define PREFETCH_HINT_STORE 1 -# define PREFETCH_HINT_STORE_STREAMED 5 -# define PREFETCH_HINT_STORE_RETAINED 7 -# define PREFETCH_HINT_PREPAREFORSTORE 30 - -/* If we have not picked out what hints to use at this point use the - standard load and store prefetch hints. */ -# ifndef PREFETCH_STORE_HINT -# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE -# endif - -/* We double everything when USE_DOUBLE is true so we do 2 prefetches to - get 64 bytes in that case. The assumption is that each individual - prefetch brings in 32 bytes. */ -# ifdef USE_DOUBLE -# define PREFETCH_CHUNK 64 -# define PREFETCH_FOR_STORE(chunk, reg) \ - pref PREFETCH_STORE_HINT, (chunk)*64(reg); \ - pref PREFETCH_STORE_HINT, ((chunk)*64)+32(reg) -# else -# define PREFETCH_CHUNK 32 -# define PREFETCH_FOR_STORE(chunk, reg) \ - pref PREFETCH_STORE_HINT, (chunk)*32(reg) -# endif - -/* MAX_PREFETCH_SIZE is the maximum size of a prefetch, it must not be less - than PREFETCH_CHUNK, the assumed size of each prefetch. If the real size - of a prefetch is greater than MAX_PREFETCH_SIZE and the PREPAREFORSTORE - hint is used, the code will not work correctly. If PREPAREFORSTORE is not - used than MAX_PREFETCH_SIZE does not matter. */ -# define MAX_PREFETCH_SIZE 128 -/* PREFETCH_LIMIT is set based on the fact that we never use an offset greater - than 5 on a STORE prefetch and that a single prefetch can never be larger - than MAX_PREFETCH_SIZE. We add the extra 32 when USE_DOUBLE is set because - we actually do two prefetches in that case, one 32 bytes after the other. */ -# ifdef USE_DOUBLE -# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + 32 + MAX_PREFETCH_SIZE -# else -# define PREFETCH_LIMIT (5 * PREFETCH_CHUNK) + MAX_PREFETCH_SIZE -# endif - -# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) \ - && ((PREFETCH_CHUNK * 4) < MAX_PREFETCH_SIZE) -/* We cannot handle this because the initial prefetches may fetch bytes that - are before the buffer being copied. We start copies with an offset - of 4 so avoid this situation when using PREPAREFORSTORE. */ -# error "PREFETCH_CHUNK is too large and/or MAX_PREFETCH_SIZE is too small." -# endif -#else /* USE_PREFETCH not defined */ -# define PREFETCH_FOR_STORE(offset, reg) -#endif - -#if __mips_isa_rev > 5 -# if (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) -# undef PREFETCH_STORE_HINT -# define PREFETCH_STORE_HINT PREFETCH_HINT_STORE_STREAMED -# endif -# define R6_CODE -#endif - -/* Allow the routine to be named something else if desired. */ -#ifndef MEMSET_NAME -# define MEMSET_NAME memset -#endif - -/* We load/store 64 bits at a time when USE_DOUBLE is true. - The C_ prefix stands for CHUNK and is used to avoid macro name - conflicts with system header files. */ - -#ifdef USE_DOUBLE -# define C_ST sd -# ifdef __MIPSEB -# define C_STHI sdl /* high part is left in big-endian */ -# else -# define C_STHI sdr /* high part is right in little-endian */ -# endif -#else -# define C_ST sw -# ifdef __MIPSEB -# define C_STHI swl /* high part is left in big-endian */ -# else -# define C_STHI swr /* high part is right in little-endian */ -# endif -#endif - -/* Bookkeeping values for 32 vs. 64 bit mode. */ -#ifdef USE_DOUBLE -# define NSIZE 8 -# define NSIZEMASK 0x3f -# define NSIZEDMASK 0x7f -#else -# define NSIZE 4 -# define NSIZEMASK 0x1f -# define NSIZEDMASK 0x3f -#endif -#define UNIT(unit) ((unit)*NSIZE) -#define UNITM1(unit) (((unit)*NSIZE)-1) - -#ifdef ANDROID_CHANGES -LEAF(MEMSET_NAME,0) -#else -LEAF(MEMSET_NAME) -#endif - - .set nomips16 -/* If the size is less than 4*NSIZE (16 or 32), go to L(lastb). Regardless of - size, copy dst pointer to v0 for the return value. */ - slti t2,a2,(4 * NSIZE) - move v0,a0 - bne t2,zero,L(lastb) - -/* If memset value is not zero, we copy it to all the bytes in a 32 or 64 - bit word. */ - PTR_SUBU a3,zero,a0 - beq a1,zero,L(set0) /* If memset value is zero no smear */ - nop - - /* smear byte into 32 or 64 bit word */ -#if ((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2) -# ifdef USE_DOUBLE - dins a1, a1, 8, 8 /* Replicate fill byte into half-word. */ - dins a1, a1, 16, 16 /* Replicate fill byte into word. */ - dins a1, a1, 32, 32 /* Replicate fill byte into dbl word. */ -# else - ins a1, a1, 8, 8 /* Replicate fill byte into half-word. */ - ins a1, a1, 16, 16 /* Replicate fill byte into word. */ -# endif -#else -# ifdef USE_DOUBLE - and a1,0xff - dsll t2,a1,8 - or a1,t2 - dsll t2,a1,16 - or a1,t2 - dsll t2,a1,32 - or a1,t2 -# else - and a1,0xff - sll t2,a1,8 - or a1,t2 - sll t2,a1,16 - or a1,t2 -# endif -#endif - -/* If the destination address is not aligned do a partial store to get it - aligned. If it is already aligned just jump to L(aligned). */ -L(set0): -#ifndef R6_CODE - andi t2,a3,(NSIZE-1) /* word-unaligned address? */ - PTR_SUBU a2,a2,t2 - beq t2,zero,L(aligned) /* t2 is the unalignment count */ - C_STHI a1,0(a0) - PTR_ADDU a0,a0,t2 -#else /* R6_CODE */ - andi t2,a0,7 -# ifdef __mips_micromips - auipc t9,%pcrel_hi(L(atable)) - addiu t9,t9,%pcrel_lo(L(atable)+4) - PTR_LSA t9,t2,t9,1 -# else - lapc t9,L(atable) - PTR_LSA t9,t2,t9,2 -# endif - jrc t9 -L(atable): - PTR_BC L(aligned) - PTR_BC L(lb7) - PTR_BC L(lb6) - PTR_BC L(lb5) - PTR_BC L(lb4) - PTR_BC L(lb3) - PTR_BC L(lb2) - PTR_BC L(lb1) -L(lb7): - sb a1,6(a0) -L(lb6): - sb a1,5(a0) -L(lb5): - sb a1,4(a0) -L(lb4): - sb a1,3(a0) -L(lb3): - sb a1,2(a0) -L(lb2): - sb a1,1(a0) -L(lb1): - sb a1,0(a0) - - li t9,NSIZE - subu t2,t9,t2 - PTR_SUBU a2,a2,t2 - PTR_ADDU a0,a0,t2 -#endif /* R6_CODE */ - -L(aligned): -/* If USE_DOUBLE is not set we may still want to align the data on a 16 - byte boundary instead of an 8 byte boundary to maximize the opportunity - of proAptiv chips to do memory bonding (combining two sequential 4 - byte stores into one 8 byte store). We know there are at least 4 bytes - left to store or we would have jumped to L(lastb) earlier in the code. */ -#ifdef DOUBLE_ALIGN - andi t2,a3,4 - PTR_SUBU a2,a2,t2 - beq t2,zero,L(double_aligned) - sw a1,0(a0) - PTR_ADDU a0,a0,t2 -L(double_aligned): -#endif - -/* Now the destination is aligned to (word or double word) aligned address - Set a2 to count how many bytes we have to copy after all the 64/128 byte - chunks are copied and a3 to the dest pointer after all the 64/128 byte - chunks have been copied. We will loop, incrementing a0 until it equals - a3. */ - andi t8,a2,NSIZEDMASK /* any whole 64-byte/128-byte chunks? */ - PTR_SUBU a3,a2,t8 /* subtract from a2 the reminder */ - beq a2,t8,L(chkw) /* if a2==t8, no 64-byte/128-byte chunks */ - PTR_ADDU a3,a0,a3 /* Now a3 is the final dst after loop */ - -/* When in the loop we may prefetch with the 'prepare to store' hint, - in this case the a0+x should not be past the "t0-32" address. This - means: for x=128 the last "safe" a0 address is "t0-160". Alternatively, - for x=64 the last "safe" a0 address is "t0-96" In the current version we - will use "prefetch hint,128(a0)", so "t0-160" is the limit. */ -#if defined(USE_PREFETCH) \ - && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) - PTR_ADDU t0,a0,a2 /* t0 is the "past the end" address */ - PTR_SUBU t9,t0,PREFETCH_LIMIT /* t9 is the "last safe pref" address */ -#endif -#if defined(USE_PREFETCH) \ - && (PREFETCH_STORE_HINT != PREFETCH_HINT_PREPAREFORSTORE) - PREFETCH_FOR_STORE (1, a0) - PREFETCH_FOR_STORE (2, a0) - PREFETCH_FOR_STORE (3, a0) -#endif - -L(loop16w): -#if defined(USE_PREFETCH) \ - && (PREFETCH_STORE_HINT == PREFETCH_HINT_PREPAREFORSTORE) - sltu v1,t9,a0 /* If a0 > t9 don't use next prefetch */ - bgtz v1,L(skip_pref) -#endif -#ifdef R6_CODE - PREFETCH_FOR_STORE (2, a0) -#else - PREFETCH_FOR_STORE (4, a0) - PREFETCH_FOR_STORE (5, a0) -#endif -L(skip_pref): - C_ST a1,UNIT(0)(a0) - C_ST a1,UNIT(1)(a0) - C_ST a1,UNIT(2)(a0) - C_ST a1,UNIT(3)(a0) - C_ST a1,UNIT(4)(a0) - C_ST a1,UNIT(5)(a0) - C_ST a1,UNIT(6)(a0) - C_ST a1,UNIT(7)(a0) - C_ST a1,UNIT(8)(a0) - C_ST a1,UNIT(9)(a0) - C_ST a1,UNIT(10)(a0) - C_ST a1,UNIT(11)(a0) - C_ST a1,UNIT(12)(a0) - C_ST a1,UNIT(13)(a0) - C_ST a1,UNIT(14)(a0) - C_ST a1,UNIT(15)(a0) - PTR_ADDIU a0,a0,UNIT(16) /* adding 64/128 to dest */ - bne a0,a3,L(loop16w) - move a2,t8 - -/* Here we have dest word-aligned but less than 64-bytes or 128 bytes to go. - Check for a 32(64) byte chunk and copy if there is one. Otherwise - jump down to L(chk1w) to handle the tail end of the copy. */ -L(chkw): - andi t8,a2,NSIZEMASK /* is there a 32-byte/64-byte chunk. */ - /* the t8 is the reminder count past 32-bytes */ - beq a2,t8,L(chk1w)/* when a2==t8, no 32-byte chunk */ - C_ST a1,UNIT(0)(a0) - C_ST a1,UNIT(1)(a0) - C_ST a1,UNIT(2)(a0) - C_ST a1,UNIT(3)(a0) - C_ST a1,UNIT(4)(a0) - C_ST a1,UNIT(5)(a0) - C_ST a1,UNIT(6)(a0) - C_ST a1,UNIT(7)(a0) - PTR_ADDIU a0,a0,UNIT(8) - -/* Here we have less than 32(64) bytes to set. Set up for a loop to - copy one word (or double word) at a time. Set a2 to count how many - bytes we have to copy after all the word (or double word) chunks are - copied and a3 to the dest pointer after all the (d)word chunks have - been copied. We will loop, incrementing a0 until a0 equals a3. */ -L(chk1w): - andi a2,t8,(NSIZE-1) /* a2 is the reminder past one (d)word chunks */ - PTR_SUBU a3,t8,a2 /* a3 is count of bytes in one (d)word chunks */ - beq a2,t8,L(lastb) - PTR_ADDU a3,a0,a3 /* a3 is the dst address after loop */ - -/* copying in words (4-byte or 8 byte chunks) */ -L(wordCopy_loop): - PTR_ADDIU a0,a0,UNIT(1) - C_ST a1,UNIT(-1)(a0) - bne a0,a3,L(wordCopy_loop) - -/* Copy the last 8 (or 16) bytes */ -L(lastb): - PTR_ADDU a3,a0,a2 /* a3 is the last dst address */ - blez a2,L(leave) -L(lastbloop): - PTR_ADDIU a0,a0,1 - sb a1,-1(a0) - bne a0,a3,L(lastbloop) -L(leave): - jr ra - - .set at -END(MEMSET_NAME) -#ifndef ANDROID_CHANGES -# ifdef _LIBC -libc_hidden_builtin_def (MEMSET_NAME) -# endif -#endif diff --git a/sysdeps/mips/memset.c b/sysdeps/mips/memset.c new file mode 100644 index 0000000000..6082a1754d --- /dev/null +++ b/sysdeps/mips/memset.c @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2024 MIPS Tech, LLC + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifdef __GNUC__ + +#undef memset + +#include + +#if _MIPS_SIM == _ABIO32 +#define SIZEOF_reg_t 4 +typedef unsigned long reg_t; +#else +#define SIZEOF_reg_t 8 +typedef unsigned long long reg_t; +#endif + +typedef struct bits8 +{ + reg_t B0:8, B1:8, B2:8, B3:8; +#if SIZEOF_reg_t == 8 + reg_t B4:8, B5:8, B6:8, B7:8; +#endif +} bits8_t; +typedef struct bits16 +{ + reg_t B0:16, B1:16; +#if SIZEOF_reg_t == 8 + reg_t B2:16, B3:16; +#endif +} bits16_t; +typedef struct bits32 +{ + reg_t B0:32; +#if SIZEOF_reg_t == 8 + reg_t B1:32; +#endif +} bits32_t; + +/* This union assumes that small structures can be in registers. If + not, then memory accesses will be done - not optimal, but ok. */ +typedef union +{ + reg_t v; + bits8_t b8; + bits16_t b16; + bits32_t b32; +} bitfields_t; + +/* This code is called when aligning a pointer or there are remaining bytes + after doing word sets. */ +static inline void * __attribute__ ((always_inline)) +do_bytes (void *a, void *retval, unsigned char fill, const unsigned long len) +{ + unsigned char *x = ((unsigned char *) a); + unsigned long i; + + for (i = 0; i < len; i++) + *x++ = fill; + + return retval; +} + +/* Pointer is aligned. */ +static void * +do_aligned_words (reg_t * a, void * retval, reg_t fill, + unsigned long words, unsigned long bytes) +{ + unsigned long i, words_by_1, words_by_16; + + words_by_1 = words % 16; + words_by_16 = words / 16; + + /* + * Note: prefetching the store memory is not beneficial on most + * cores since the ls/st unit has store buffers that will be filled + * before the cache line is actually needed. + * + * Also, using prepare-for-store cache op is problematic since we + * don't know the implementation-defined cache line length and we + * don't want to touch unintended memory. + */ + for (i = 0; i < words_by_16; i++) + { + a[0] = fill; + a[1] = fill; + a[2] = fill; + a[3] = fill; + a[4] = fill; + a[5] = fill; + a[6] = fill; + a[7] = fill; + a[8] = fill; + a[9] = fill; + a[10] = fill; + a[11] = fill; + a[12] = fill; + a[13] = fill; + a[14] = fill; + a[15] = fill; + a += 16; + } + + /* do remaining words. */ + for (i = 0; i < words_by_1; i++) + *a++ = fill; + + /* mop up any remaining bytes. */ + return do_bytes (a, retval, fill, bytes); +} + +void * +inhibit_loop_to_libcall +memset (void *a, int ifill, size_t len) +{ + unsigned long bytes, words; + bitfields_t fill; + void *retval = (void *) a; + + /* shouldn't hit that often. */ + if (len < 16) + return do_bytes (a, retval, ifill, len); + + /* Align the pointer to word/dword alignment. + Note that the pointer is only 32-bits for o32/n32 ABIs. For + n32, loads are done as 64-bit while address remains 32-bit. */ + bytes = ((unsigned long) a) % (sizeof (reg_t) * 2); + if (bytes) + { + bytes = (sizeof (reg_t) * 2 - bytes); + if (bytes > len) + bytes = len; + do_bytes (a, retval, ifill, bytes); + if (len == bytes) + return retval; + len -= bytes; + a = (void *) (((unsigned char *) a) + bytes); + } + + /* Create correct fill value for reg_t sized variable. */ + if (ifill != 0) + { + fill.b8.B0 = (unsigned char) ifill; + fill.b8.B1 = fill.b8.B0; + fill.b16.B1 = fill.b16.B0; +#if SIZEOF_reg_t == 8 + fill.b32.B1 = fill.b32.B0; +#endif + } + else + fill.v = 0; + + words = len / sizeof (reg_t); + bytes = len % sizeof (reg_t); + return do_aligned_words (a, retval, fill.v, words, bytes); +} + + +libc_hidden_builtin_def (memset) + +#else +#include +#endif From patchwork Wed Jun 18 14:33:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jovan Dmitrovic X-Patchwork-Id: 114673 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9C2A83882020 for ; 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Fix prefetching in core loop to avoid exceeding the operated upon memory region. Revert accidentally changed prefetch-hint back to streaming mode. Refactor various bits and provide pre-processor checks to allow parameters to be overridden from compiler command line. Cherry-picked 132e0bbbbed01f95ec88b68b5f7f2056f6125531 from https://github.com/MIPS/glibc Signed-off-by: Faraz Shahbazker Signed-off-by: Aleksandar Rakic Signed-off-by: Jovan Dmitrović --- sysdeps/mips/memcpy.c | 188 +++++++++++++++++++++++++----------------- 1 file changed, 111 insertions(+), 77 deletions(-) -- 2.34.1 diff --git a/sysdeps/mips/memcpy.c b/sysdeps/mips/memcpy.c index 8c3aec7b36..798e991f6d 100644 --- a/sysdeps/mips/memcpy.c +++ b/sysdeps/mips/memcpy.c @@ -1,37 +1,29 @@ -/* - * Copyright (C) 2024 MIPS Tech, LLC - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. -*/ +/* Copyright (C) 2024 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Wave Computing + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + . */ #ifdef __GNUC__ #undef memcpy /* Typical observed latency in cycles in fetching from DRAM. */ -#define LATENCY_CYCLES 63 +#ifndef LATENCY_CYCLES + #define LATENCY_CYCLES 63 +#endif /* Pre-fetch performance is subject to accurate prefetch ahead, which in turn depends on both the cache-line size and the amount @@ -48,30 +40,42 @@ #define LATENCY_CYCLES 150 #elif defined(_MIPS_TUNE_I6400) || defined(_MIPS_TUNE_I6500) #define CACHE_LINE 64 - #define BLOCK_CYCLES 16 + #define BLOCK_CYCLES 15 #elif defined(_MIPS_TUNE_P6600) #define CACHE_LINE 32 - #define BLOCK_CYCLES 12 + #define BLOCK_CYCLES 15 #elif defined(_MIPS_TUNE_INTERAPTIV) || defined(_MIPS_TUNE_INTERAPTIV_MR2) #define CACHE_LINE 32 #define BLOCK_CYCLES 30 #else - #define CACHE_LINE 32 - #define BLOCK_CYCLES 11 + #ifndef CACHE_LINE + #define CACHE_LINE 32 + #endif + #ifndef BLOCK_CYCLES + #ifdef __nanomips__ + #define BLOCK_CYCLES 20 + #else + #define BLOCK_CYCLES 11 + #endif + #endif #endif /* Pre-fetch look ahead = ceil (latency / block-cycles) */ #define PREF_AHEAD (LATENCY_CYCLES / BLOCK_CYCLES \ + ((LATENCY_CYCLES % BLOCK_CYCLES) == 0 ? 0 : 1)) -/* Unroll-factor, controls how many words at a time in the core loop. */ -#define BLOCK (CACHE_LINE == 128 ? 16 : 8) +/* The unroll-factor controls how many words at a time in the core loop. */ +#ifndef BLOCK_SIZE + #define BLOCK_SIZE (CACHE_LINE == 128 ? 16 : 8) +#elif BLOCK_SIZE != 8 && BLOCK_SIZE != 16 + #error "BLOCK_SIZE must be 8 or 16" +#endif #define __overloadable #if !defined(UNALIGNED_INSTR_SUPPORT) /* does target have unaligned lw/ld/ualw/uald instructions? */ #define UNALIGNED_INSTR_SUPPORT 0 -#if (__mips_isa_rev < 6 && !defined(__mips1)) +#if (__mips_isa_rev < 6 && !defined(__mips1)) || defined(__nanomips__) #undef UNALIGNED_INSTR_SUPPORT #define UNALIGNED_INSTR_SUPPORT 1 #endif @@ -79,17 +83,35 @@ #if !defined(HW_UNALIGNED_SUPPORT) /* Does target have hardware support for unaligned accesses? */ #define HW_UNALIGNED_SUPPORT 0 - #if __mips_isa_rev >= 6 + #if __mips_isa_rev >= 6 && !defined(__nanomips__) #undef HW_UNALIGNED_SUPPORT #define HW_UNALIGNED_SUPPORT 1 #endif #endif -#define ENABLE_PREFETCH 1 + +#ifndef ENABLE_PREFETCH + #define ENABLE_PREFETCH 1 +#endif + +#ifndef ENABLE_PREFETCH_CHECK + #define ENABLE_PREFETCH_CHECK 0 +#endif + #if ENABLE_PREFETCH - #define PREFETCH(addr) __builtin_prefetch (addr, 0, 0) -#else + #if ENABLE_PREFETCH_CHECK +#include +static char *limit; +#define PREFETCH(addr) \ + do { \ + assert ((char *)(addr) < limit); \ + __builtin_prefetch ((addr), 0, 1); \ + } while (0) +#else /* ENABLE_PREFETCH_CHECK */ + #define PREFETCH(addr) __builtin_prefetch (addr, 0, 1) + #endif /* ENABLE_PREFETCH_CHECK */ +#else /* ENABLE_PREFETCH */ #define PREFETCH(addr) -#endif +#endif /* ENABLE_PREFETCH */ #include @@ -99,17 +121,18 @@ typedef struct { reg_t B0:8, B1:8, B2:8, B3:8, B4:8, B5:8, B6:8, B7:8; } bits_t; -#else +#else /* __mips64 */ typedef unsigned long reg_t; typedef struct { reg_t B0:8, B1:8, B2:8, B3:8; } bits_t; -#endif +#endif /* __mips64 */ -#define CACHE_LINES_PER_BLOCK ((BLOCK * sizeof (reg_t) > CACHE_LINE) ? \ - (BLOCK * sizeof (reg_t) / CACHE_LINE) \ - : 1) +#define CACHE_LINES_PER_BLOCK \ + ((BLOCK_SIZE * sizeof (reg_t) > CACHE_LINE) \ + ? (BLOCK_SIZE * sizeof (reg_t) / CACHE_LINE) \ + : 1) typedef union { @@ -120,7 +143,7 @@ typedef union #define DO_BYTE(a, i) \ a[i] = bw.b.B##i; \ len--; \ - if(!len) return ret; \ + if (!len) return ret; \ /* This code is called when aligning a pointer, there are remaining bytes after doing word compares, or architecture does not have some form @@ -148,7 +171,7 @@ do_bytes_remaining (void *a, const void *b, unsigned long len, void *ret) { unsigned char *x = (unsigned char *) a; bitfields_t bw; - if(len > 0) + if (len > 0) { bw.v = *(reg_t *)b; DO_BYTE(x, 0); @@ -159,7 +182,7 @@ do_bytes_remaining (void *a, const void *b, unsigned long len, void *ret) DO_BYTE(x, 4); DO_BYTE(x, 5); DO_BYTE(x, 6); -#endif +#endif /* __mips64 */ } return ret; } @@ -170,7 +193,7 @@ do_words_remaining (reg_t *a, const reg_t *b, unsigned long words, { /* Use a set-back so that load/stores have incremented addresses in order to promote bonding. */ - int off = (BLOCK - words); + int off = (BLOCK_SIZE - words); a -= off; b -= off; switch (off) @@ -182,7 +205,7 @@ do_words_remaining (reg_t *a, const reg_t *b, unsigned long words, case 5: a[5] = b[5]; // Fall through case 6: a[6] = b[6]; // Fall through case 7: a[7] = b[7]; // Fall through -#if BLOCK==16 +#if BLOCK_SIZE==16 case 8: a[8] = b[8]; // Fall through case 9: a[9] = b[9]; // Fall through case 10: a[10] = b[10]; // Fall through @@ -191,9 +214,9 @@ do_words_remaining (reg_t *a, const reg_t *b, unsigned long words, case 13: a[13] = b[13]; // Fall through case 14: a[14] = b[14]; // Fall through case 15: a[15] = b[15]; -#endif +#endif /* BLOCK_SIZE==16 */ } - return do_bytes_remaining (a + BLOCK, b + BLOCK, bytes, ret); + return do_bytes_remaining (a + BLOCK_SIZE, b + BLOCK_SIZE, bytes, ret); } #if !HW_UNALIGNED_SUPPORT @@ -210,7 +233,7 @@ do_uwords_remaining (struct ulw *a, const reg_t *b, unsigned long words, { /* Use a set-back so that load/stores have incremented addresses in order to promote bonding. */ - int off = (BLOCK - words); + int off = (BLOCK_SIZE - words); a -= off; b -= off; switch (off) @@ -222,7 +245,7 @@ do_uwords_remaining (struct ulw *a, const reg_t *b, unsigned long words, case 5: a[5].uli = b[5]; // Fall through case 6: a[6].uli = b[6]; // Fall through case 7: a[7].uli = b[7]; // Fall through -#if BLOCK==16 +#if BLOCK_SIZE==16 case 8: a[8].uli = b[8]; // Fall through case 9: a[9].uli = b[9]; // Fall through case 10: a[10].uli = b[10]; // Fall through @@ -231,9 +254,9 @@ do_uwords_remaining (struct ulw *a, const reg_t *b, unsigned long words, case 13: a[13].uli = b[13]; // Fall through case 14: a[14].uli = b[14]; // Fall through case 15: a[15].uli = b[15]; -#endif +#endif /* BLOCK_SIZE==16 */ } - return do_bytes_remaining (a + BLOCK, b + BLOCK, bytes, ret); + return do_bytes_remaining (a + BLOCK_SIZE, b + BLOCK_SIZE, bytes, ret); } /* The first pointer is not aligned while second pointer is. */ @@ -242,13 +265,19 @@ unaligned_words (struct ulw *a, const reg_t * b, unsigned long words, unsigned long bytes, void *ret) { unsigned long i, words_by_block, words_by_1; - words_by_1 = words % BLOCK; - words_by_block = words / BLOCK; + words_by_1 = words % BLOCK_SIZE; + words_by_block = words / BLOCK_SIZE; + for (; words_by_block > 0; words_by_block--) { - if (words_by_block >= PREF_AHEAD - CACHE_LINES_PER_BLOCK) + /* This condition is deliberately conservative. One could theoretically + pre-fetch another time around in some cases without crossing the page + boundary at the limit, but checking for the right conditions here is + too expensive to be worth it. */ + if (words_by_block > PREF_AHEAD) for (i = 0; i < CACHE_LINES_PER_BLOCK; i++) - PREFETCH (b + (BLOCK / CACHE_LINES_PER_BLOCK) * (PREF_AHEAD + i)); + PREFETCH (b + ((BLOCK_SIZE / CACHE_LINES_PER_BLOCK) + * (PREF_AHEAD + i))); reg_t y0 = b[0], y1 = b[1], y2 = b[2], y3 = b[3]; reg_t y4 = b[4], y5 = b[5], y6 = b[6], y7 = b[7]; @@ -260,7 +289,7 @@ unaligned_words (struct ulw *a, const reg_t * b, a[5].uli = y5; a[6].uli = y6; a[7].uli = y7; -#if BLOCK==16 +#if BLOCK_SIZE==16 y0 = b[8], y1 = b[9], y2 = b[10], y3 = b[11]; y4 = b[12], y5 = b[13], y6 = b[14], y7 = b[15]; a[8].uli = y0; @@ -271,16 +300,16 @@ unaligned_words (struct ulw *a, const reg_t * b, a[13].uli = y5; a[14].uli = y6; a[15].uli = y7; -#endif - a += BLOCK; - b += BLOCK; +#endif /* BLOCK_SIZE==16 */ + a += BLOCK_SIZE; + b += BLOCK_SIZE; } /* Mop up any remaining bytes. */ return do_uwords_remaining (a, b, words_by_1, bytes, ret); } -#else +#else /* !UNALIGNED_INSTR_SUPPORT */ /* No HW support or unaligned lw/ld/ualw/uald instructions. */ static void * @@ -320,13 +349,15 @@ aligned_words (reg_t * a, const reg_t * b, unsigned long words, unsigned long bytes, void *ret) { unsigned long i, words_by_block, words_by_1; - words_by_1 = words % BLOCK; - words_by_block = words / BLOCK; + words_by_1 = words % BLOCK_SIZE; + words_by_block = words / BLOCK_SIZE; + for (; words_by_block > 0; words_by_block--) { - if(words_by_block >= PREF_AHEAD - CACHE_LINES_PER_BLOCK) + if (words_by_block > PREF_AHEAD) for (i = 0; i < CACHE_LINES_PER_BLOCK; i++) - PREFETCH (b + ((BLOCK / CACHE_LINES_PER_BLOCK) * (PREF_AHEAD + i))); + PREFETCH (b + ((BLOCK_SIZE / CACHE_LINES_PER_BLOCK) + * (PREF_AHEAD + i))); reg_t x0 = b[0], x1 = b[1], x2 = b[2], x3 = b[3]; reg_t x4 = b[4], x5 = b[5], x6 = b[6], x7 = b[7]; @@ -338,7 +369,7 @@ aligned_words (reg_t * a, const reg_t * b, a[5] = x5; a[6] = x6; a[7] = x7; -#if BLOCK==16 +#if BLOCK_SIZE==16 x0 = b[8], x1 = b[9], x2 = b[10], x3 = b[11]; x4 = b[12], x5 = b[13], x6 = b[14], x7 = b[15]; a[8] = x0; @@ -349,9 +380,9 @@ aligned_words (reg_t * a, const reg_t * b, a[13] = x5; a[14] = x6; a[15] = x7; -#endif - a += BLOCK; - b += BLOCK; +#endif /* BLOCK_SIZE==16 */ + a += BLOCK_SIZE; + b += BLOCK_SIZE; } /* mop up any remaining bytes. */ @@ -363,13 +394,16 @@ memcpy (void *a, const void *b, size_t len) __overloadable { unsigned long bytes, words, i; void *ret = a; +#if ENABLE_PREFETCH_CHECK + limit = (char *)b + len; +#endif /* ENABLE_PREFETCH_CHECK */ /* shouldn't hit that often. */ if (len <= 8) return do_bytes (a, b, len, a); /* Start pre-fetches ahead of time. */ - if (len > CACHE_LINE * (PREF_AHEAD - 1)) - for (i = 1; i < PREF_AHEAD - 1; i++) + if (len > CACHE_LINE * PREF_AHEAD) + for (i = 1; i < PREF_AHEAD; i++) PREFETCH ((char *)b + CACHE_LINE * i); else for (i = 1; i < len / CACHE_LINE; i++) @@ -400,12 +434,12 @@ memcpy (void *a, const void *b, size_t len) __overloadable #if HW_UNALIGNED_SUPPORT /* treat possible unaligned first pointer as aligned. */ return aligned_words (a, b, words, bytes, ret); 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you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. + +# The GNU C Library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. + +# You should have received a copy of the GNU Lesser General Public +# License along with the GNU C Library; if not, see +# . + +# usage: cross-test-qemu.sh HOST COMMAND ... +# Run with --help flag to get more detailed help. + +progname="$(basename $0)" + +usage="usage: ${progname} [--ssh SSH] HOST COMMAND ..." +timeoutfactor=$TIMEOUTFACTOR +addon_libpath="" +while [ $# -gt 0 ]; do + case "$1" in + + "--timeoutfactor") + shift + if [ $# -lt 1 ]; then + break + fi + timeoutfactor="$1" + ;; + + "--addon-libpath") + shift + if [ $# -lt 1 ]; then + break + fi + addon_libpath="$1" + ;; + + "--help") + echo "$usage" + echo "$help" + exit 0 + ;; + + *) + break + ;; + esac + shift +done + +if [ $# -lt 1 ]; then + echo "$usage" >&2 + echo "Type '${progname} --help' for more detailed help." >&2 + exit 1 +fi + +emulator="$1"; shift +envpat="[:alpha:]*=.*" +ldpat=".*/.*ld.*\.so.*" +lgccpat="libgcc_s.so.1" +libpat="--library-path" +ldpath="" +lgccpath="" +envlist="" +liblist="" +command="" +toolchain=`dirname \`dirname $emulator\`` +target=`ls $toolchain | grep -e linux-gnu` +# Print the sequence of arguments as strings properly quoted for the +# Bourne shell, separated by spaces. +bourne_quote () +{ + local arg qarg libflag variant + libflag=0 + + for arg in $@; do + if [ "x$done" != "x" ]; then + command="$command $arg" + elif [[ $arg =~ $envpat ]]; then + if [ -z $envlist ]; then + envlist="$arg" + else + envlist="$arg,$envlist" + fi + elif [[ $arg =~ $ldpat ]]; then + ldfile=`basename $arg` + variant=`basename \`dirname \\\`dirname $arg\\\`\`` + libdir=${variant##*_} + variant=${variant%_*} + variant=${variant#obj_} + ldpath=$toolchain/sysroot/$variant + if [ ! -f $ldpath/$libdir/$ldfile ]; then + ldpath=`dirname $arg` + fi + lgccpath=$toolchain/$target/lib/$variant/$libdir + liblist="$ldpath:$lgccpath:$liblist" + elif [[ $arg =~ $libpat ]]; then + libflag=1 + elif [ $libflag -ne 0 ]; then + liblist="$arg:$liblist" + libflag=0 + elif [ "x$arg" != "xenv" ]; then + if [[ $arg =~ "tst-" ]]; then + if [ -f $arg ]; then + done=1 + fi + fi + command="$command $arg" + fi + done +} + +# Transform the current argument list into a properly quoted Bourne shell +# command string. +bourne_quote "$@" + +liblist=$addon_libpath:$liblist +liblist=`tr -s : <<< $liblist` +liblist=${liblist#:*} +liblist=${liblist%*:} + +if [ "x$liblist" != "x" ]; then + LIBPATH_OPT="-E LD_LIBRARY_PATH=$liblist" +fi + +if [ "x$envlist" != "x" ]; then + ENV_OPT="-E $envlist" +fi + +if [ "x$ldpath" != "x" ]; then + LDPATH_OPT="-L $ldpath" +fi + +if [ "x$timeoutfactor" != "x" ]; then + $emulator $LDPATH_OPT $LIBPATH_OPT $ENV_OPT $command & + pid=$! + trap "kill -SIGINT $pid" SIGALRM + sleep $timeoutfactor && kill -SIGALRM $$ + exit 1 +else + $emulator $LDPATH_OPT $LIBPATH_OPT $ENV_OPT $command +fi + From patchwork Wed Jun 18 14:33:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jovan Dmitrovic X-Patchwork-Id: 114675 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A4702388203B for ; Wed, 18 Jun 2025 14:36:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A4702388203B Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=htecgroup.com header.i=@htecgroup.com header.a=rsa-sha256 header.s=selector1 header.b=QhuHca6y X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazlp170100001.outbound.protection.outlook.com [IPv6:2a01:111:f403:c200::1]) by sourceware.org (Postfix) with ESMTPS id 8F2673865C3C for ; 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Wed, 18 Jun 2025 14:33:51 +0000 From: Jovan Dmitrovic To: "libc-alpha@sourceware.org" CC: Djordje Todorovic , Joseph Myers , Adhemerval Zanella Netto , Jovan Dmitrovic Subject: [PATCH v2 8/8] mips: Remove strcmp.S Thread-Topic: [PATCH v2 8/8] mips: Remove strcmp.S Thread-Index: AQHb4F4C/i70efc1gk68+qFcWvtz0Q== Date: Wed, 18 Jun 2025 14:33:51 +0000 Message-ID: <20250618143327.2665823-9-jovan.dmitrovic@htecgroup.com> References: <20250618143327.2665823-1-jovan.dmitrovic@htecgroup.com> In-Reply-To: <20250618143327.2665823-1-jovan.dmitrovic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PAVPR09MB6451:EE_|PAWPR09MB6834:EE_ x-ms-office365-filtering-correlation-id: ca86feb5-b6a9-45e4-d516-08ddae752576 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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Suggested-by: Joseph Myers Signed-off-by: Jovan Dmitrović --- sysdeps/mips/Makefile | 4 + sysdeps/mips/strcmp.S | 249 ------------------------------------------ 2 files changed, 4 insertions(+), 249 deletions(-) delete mode 100644 sysdeps/mips/strcmp.S -- 2.34.1 diff --git a/sysdeps/mips/Makefile b/sysdeps/mips/Makefile index 17ddc2a97c..d453c9aa90 100644 --- a/sysdeps/mips/Makefile +++ b/sysdeps/mips/Makefile @@ -17,6 +17,10 @@ CPPFLAGS-crti.S += $(pic-ccflag) CPPFLAGS-crtn.S += $(pic-ccflag) endif +ifeq ($(subdir),string) +CFLAGS-strcmp.c += -funroll-loops +endif + ASFLAGS-.os += $(pic-ccflag) # libc.a and libc_p.a must be compiled with -fPIE/-fpie for static PIE. diff --git a/sysdeps/mips/strcmp.S b/sysdeps/mips/strcmp.S deleted file mode 100644 index b599d5d7ec..0000000000 --- a/sysdeps/mips/strcmp.S +++ /dev/null @@ -1,249 +0,0 @@ -/* Copyright (C) 2014-2025 Free Software Foundation, Inc. - This file is part of the GNU C Library. - - The GNU C Library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - The GNU C Library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with the GNU C Library. If not, see - . */ - -#ifdef ANDROID_CHANGES -# include "machine/asm.h" -# include "machine/regdef.h" -#elif _LIBC -# include -# include -# include -#elif defined _COMPILING_NEWLIB -# include "machine/asm.h" -# include "machine/regdef.h" -#else -# include -# include -#endif - -/* Technically strcmp should not read past the end of the strings being - compared. We will read a full word that may contain excess bits beyond - the NULL string terminator but unless ENABLE_READAHEAD is set, we will not - read the next word after the end of string. Setting ENABLE_READAHEAD will - improve performance but is technically illegal based on the definition of - strcmp. */ -#ifdef ENABLE_READAHEAD -# define DELAY_READ -#else -# define DELAY_READ nop -#endif - -/* Testing on a little endian machine showed using CLZ was a - performance loss, so we are not turning it on by default. */ -#if defined(ENABLE_CLZ) && (__mips_isa_rev > 1) -# define USE_CLZ -#endif - -/* Some asm.h files do not have the L macro definition. */ -#ifndef L -# if _MIPS_SIM == _ABIO32 -# define L(label) $L ## label -# else -# define L(label) .L ## label -# endif -#endif - -/* Some asm.h files do not have the PTR_ADDIU macro definition. */ -#ifndef PTR_ADDIU -# ifdef USE_DOUBLE -# define PTR_ADDIU daddiu -# else -# define PTR_ADDIU addiu -# endif -#endif - -/* Allow the routine to be named something else if desired. */ -#ifndef STRCMP_NAME -# define STRCMP_NAME strcmp -#endif - -#ifdef ANDROID_CHANGES -LEAF(STRCMP_NAME, 0) -#else -LEAF(STRCMP_NAME) -#endif - .set nomips16 - .set noreorder - - or t0, a0, a1 - andi t0,0x3 - bne t0, zero, L(byteloop) - -/* Both strings are 4 byte aligned at this point. */ - - lui t8, 0x0101 - ori t8, t8, 0x0101 - lui t9, 0x7f7f - ori t9, 0x7f7f - -#define STRCMP32(OFFSET) \ - lw v0, OFFSET(a0); \ - lw v1, OFFSET(a1); \ - subu t0, v0, t8; \ - bne v0, v1, L(worddiff); \ - nor t1, v0, t9; \ - and t0, t0, t1; \ - bne t0, zero, L(returnzero) - -L(wordloop): - STRCMP32(0) - DELAY_READ - STRCMP32(4) - DELAY_READ - STRCMP32(8) - DELAY_READ - STRCMP32(12) - DELAY_READ - STRCMP32(16) - DELAY_READ - STRCMP32(20) - DELAY_READ - STRCMP32(24) - DELAY_READ - STRCMP32(28) - PTR_ADDIU a0, a0, 32 - b L(wordloop) - PTR_ADDIU a1, a1, 32 - -L(returnzero): - j ra - move v0, zero - -L(worddiff): -#ifdef USE_CLZ - subu t0, v0, t8 - nor t1, v0, t9 - and t1, t0, t1 - xor t0, v0, v1 - or t0, t0, t1 -# if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ - wsbh t0, t0 - rotr t0, t0, 16 -# endif - clz t1, t0 - and t1, 0xf8 -# if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ - neg t1 - addu t1, 24 -# endif - rotrv v0, v0, t1 - rotrv v1, v1, t1 - and v0, v0, 0xff - and v1, v1, 0xff - j ra - subu v0, v0, v1 -#else /* USE_CLZ */ -# if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ - andi t0, v0, 0xff - beq t0, zero, L(wexit01) - andi t1, v1, 0xff - bne t0, t1, L(wexit01) - - srl t8, v0, 8 - srl t9, v1, 8 - andi t8, t8, 0xff - beq t8, zero, L(wexit89) - andi t9, t9, 0xff - bne t8, t9, L(wexit89) - - srl t0, v0, 16 - srl t1, v1, 16 - andi t0, t0, 0xff - beq t0, zero, L(wexit01) - andi t1, t1, 0xff - bne t0, t1, L(wexit01) - - srl t8, v0, 24 - srl t9, v1, 24 -# else /* __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ */ - srl t0, v0, 24 - beq t0, zero, L(wexit01) - srl t1, v1, 24 - bne t0, t1, L(wexit01) - - srl t8, v0, 16 - srl t9, v1, 16 - andi t8, t8, 0xff - beq t8, zero, L(wexit89) - andi t9, t9, 0xff - bne t8, t9, L(wexit89) - - srl t0, v0, 8 - srl t1, v1, 8 - andi t0, t0, 0xff - beq t0, zero, L(wexit01) - andi t1, t1, 0xff - bne t0, t1, L(wexit01) - - andi t8, v0, 0xff - andi t9, v1, 0xff -# endif /* __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ */ - -L(wexit89): - j ra - subu v0, t8, t9 -L(wexit01): - j ra - subu v0, t0, t1 -#endif /* USE_CLZ */ - -/* It might seem better to do the 'beq' instruction between the two 'lbu' - instructions so that the nop is not needed but testing showed that this - code is actually faster (based on glibc strcmp test). */ -#define BYTECMP01(OFFSET) \ - lbu v0, OFFSET(a0); \ - lbu v1, OFFSET(a1); \ - beq v0, zero, L(bexit01); \ - nop; \ - bne v0, v1, L(bexit01) - -#define BYTECMP89(OFFSET) \ - lbu t8, OFFSET(a0); \ - lbu t9, OFFSET(a1); \ - beq t8, zero, L(bexit89); \ - nop; \ - bne t8, t9, L(bexit89) - -L(byteloop): - BYTECMP01(0) - BYTECMP89(1) - BYTECMP01(2) - BYTECMP89(3) - BYTECMP01(4) - BYTECMP89(5) - BYTECMP01(6) - BYTECMP89(7) - PTR_ADDIU a0, a0, 8 - b L(byteloop) - PTR_ADDIU a1, a1, 8 - -L(bexit01): - j ra - subu v0, v0, v1 -L(bexit89): - j ra - subu v0, t8, t9 - - .set at - .set reorder - -END(STRCMP_NAME) -#ifndef ANDROID_CHANGES -# ifdef _LIBC -libc_hidden_builtin_def (STRCMP_NAME) -# endif -#endif