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Thu, 12 Jun 2025 14:29:10 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2365deb049asm1796485ad.182.2025.06.12.14.29.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 14:29:10 -0700 (PDT) From: Deepak Gupta Date: Thu, 12 Jun 2025 14:29:08 -0700 Subject: [PATCH RFC] RISCV: insert zimop instruction at the start MIME-Version: 1.0 Message-Id: <20250612-glibc_zimop-v1-1-88f15a37d233@rivosinc.com> X-B4-Tracking: v=1; b=H4sIAKNGS2gC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1MDM0Mj3fSczKTk+KrM3PwCXRMLAwsLA1MLwySjJCWgjoKi1LTMCrBp0Up Bbs5KsbW1ANd1B5ViAAAA To: libc-alpha@sourceware.org Cc: Deepak Gupta X-Mailer: b4 0.13.0 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~patchwork=sourceware.org@sourceware.org RVA23 mandates that CPU must implement zimop and zcmop extensions. These extensions are termed as "may be operations" to signify that some instructions might be leveraged by some future extensions to turn into different operations. Unless those extensions are used for codegen, there is no way to ensure that compiled software has zimop/zcmop instruction in them. Without any software using these instructions, there is no way to ensure that target hardware is RVA23 compatible. zicfiss extension converts some of the zimop instructions into shadow stack instructions. Support for shadow stack is still in the flux. This patch ensures that if compiler supports shadow stack codegen then sspush/sspopchk instructions are at the start when userspace starts life. Kernel doesn't enable shadow stack for userspace by default. Userspace will issue shadow stack enable prtctls to kernel. Thus always these (sspush/sspopchk) instructions will default to zimop behavior. Note that this is not a backward hardware compatible change. Signed-off-by: Deepak Gupta --- RVA23 mandates that CPU must implement zimop and zcmop extensions. These extensions are termed as "may be operations" to signify that some instructions might be leveraged by some future extensions to turn into different operations. Unless those extensions are used for codegen, there is no way to ensure that compiled software has zimop/zcmop instruction in them. Without any software using these instructions, there is no way to ensure that target hardware is RVA23 compatible. zicfiss extension converts some of the zimop instructions into shadow stack instructions. Support for shadow stack is still in the flux. This patch ensures that if compiler supports shadow stack codegen then sspush/sspopchk instructions are at the start when userspace starts life. Kernel doesn't enable shadow stack for userspace by default. Userspace will issue shadow stack enable prctls to kernel. Thus always these (sspush/sspopchk) instructions will default to zimop behavior. Note that this is not a backward hardware compatible change. --- sysdeps/riscv/dl-machine.h | 10 ++++++++++ 1 file changed, 10 insertions(+) --- base-commit: 77930e0447e0b37a129db0e13c6c6f5e60a3019e change-id: 20250612-glibc_zimop-480880581b2b -- - debug diff --git a/sysdeps/riscv/dl-machine.h b/sysdeps/riscv/dl-machine.h index dcc3e0883b..162b6034ea 100644 --- a/sysdeps/riscv/dl-machine.h +++ b/sysdeps/riscv/dl-machine.h @@ -53,6 +53,15 @@ || (__WORDSIZE == 64 && (type) == R_RISCV_TLS_TPREL64))) \ | (ELF_RTYPE_CLASS_COPY * ((type) == R_RISCV_COPY))) + +#ifdef __riscv_zicfiss +#define INSERT_ZIMOP \ + sspush x1 \ + sspop x1 +#else +#define INSERT_ZIMOP +#endif + /* Return nonzero iff ELF header is compatible with the running host. */ static inline int __attribute_used__ elf_machine_matches_host (const ElfW(Ehdr) *ehdr) @@ -102,6 +111,7 @@ elf_machine_dynamic (void) #define RTLD_START asm (\ ".text\n\ " _RTLD_PROLOGUE (ENTRY_POINT) "\ + INSERT_ZIMOP \ mv a0, sp\n\ jal _dl_start\n\ " _RTLD_PROLOGUE (_dl_start_user) "\