/* Copyright 2009 DJ Delorie
   Released under the terms of the GNU General Public License,
   either version 2 or, at your choice, any later version.
   http://www.delorie.com/electronics/sdram/
 */

`timescale 1ns / 1ps

module mcu_testbed ();

/* m32c/87 at 5.0v: tCYC = 31.25 (32 MHz) */
/* m32c/87 at 3.3v: tCYC = 41.00 (24 MHz) */
//parameter tcyc = 1000.0 / (24 * 2) * 2;
parameter tcyc = 1000.0 / (24 * 2);
//parameter tcyc = 1000 / (32 * 2);

reg         bclk;
reg 	    reset;
 	    

reg  [23:0] test_addr;
reg  [15:0] test_data;
wire [15:0] test_dataW;
reg 	    test_ncs;
reg 	    test_nrd;
reg 	    test_nwrh;
reg 	    test_nwrl;
wire        test_ready;

reg [7:0]   op;

wire        sdram_cke;
wire        sdram_clk;
wire        sdram_cs_n;
wire        sdram_we_n;
wire        sdram_cas_n;
wire        sdram_ras_n;
wire  [1:0] sdram_dqm;
wire [11:0] sdram_adr;
wire  [1:0] sdram_ba;
wire [15:0] sdram_dq;
   

top1 UUT (
	.f_io_0(reset),

	.f_io_1(test_ncs),
	.c_wrl(test_nwrl),
	.c_wrh(test_nwrh),
	.c_rd(test_nrd),
	.c_rdy(test_ready),
	.c_bclk(bclk),

	.c_addr(test_addr),
	.c_data(test_dataW),

	.r_ba(sdram_ba),
	.r_clk(sdram_clk),
	.r_cke(sdram_cke),
	.r_cs(sdram_cs_n),
	.r_ras(sdram_ras_n),
	.r_cas(sdram_cas_n),
	.r_we(sdram_we_n),
	.r_dqm(sdram_dqm),

	.r_addr(sdram_adr),
	.r_data(sdram_dq)
);

mt48lc8m16a2 sdram(
	.Dq(sdram_dq),
	.Addr(sdram_adr),
	.Ba(sdram_ba),
	.Clk(sdram_clk),
	.Cke(sdram_cke),
	.Cs_n(sdram_cs_n),
	.Ras_n(sdram_ras_n),
	.Cas_n(sdram_cas_n),
	.We_n(sdram_we_n),
	.Dqm(sdram_dqm)
);

assign test_dataW = test_data;

/* These always start just AFTER the rising edge of the clock.  */

task mcu_write;
   input [23:0] address;
   input [15:0] data;
   input [1:0] 	bhl;
   begin
      op = 87;
      test_addr = address;
      test_ncs = 0;

      #tcyc bclk = 0;
      test_data = data;

      #tcyc bclk = 1;
      test_nwrh = bhl[0];
      test_nwrl = bhl[1];

      #tcyc bclk = 0;

      while (~test_ready) begin
	 #tcyc bclk = 1;
	 #tcyc bclk = 0;
      end
      test_nwrh = 1;
      test_nwrl = 1;

      #tcyc bclk = 1;
      test_addr = 24'hzzzzzz;
      test_data = 16'hzzzz;
      op = 32;
   end
endtask // mcu_write

task mcu_read;
   input [23:0] address;
   input [15:0] xdata;
   begin
      op = 82;
      test_addr = address;
      test_ncs = 0;

      #tcyc bclk = 0;
      #14 test_nrd = 0;

      #(tcyc-14) bclk = 1;

      #tcyc bclk = 0;
      while (~test_ready) begin
	 #tcyc bclk = 1;
	 #tcyc bclk = 0;
      end

      #tcyc bclk = 1;
      $display("INFO: %t: read: %h vs %h\n", $time, test_dataW, xdata);
      if (test_dataW !== xdata) begin
	 $display("ERROR: %t: read error: %h vs %h\n", $time, test_dataW, xdata);
	 
      end

      test_addr = 24'hzzzzzz;
      test_nrd = 1;
      op = 32;
   end
endtask // mcu_write

task mcu_tick;
   begin
      test_ncs = 1;
      #tcyc bclk = 0;
      #tcyc bclk = 1;
   end
endtask // mcu_write

initial begin
   # 2000000000;
   /*$finish;*/
   
end

initial begin  
   #100000 $dumpvars;
   /*#0 $dumpvars;*/
end

integer i;


initial begin

   op = 32;
   test_ncs = 1;
   test_nrd = 1;
   test_nwrl = 1;
   test_nwrh = 1;
   test_addr = 24'hzzzz;
   test_data = 16'hzzzz;

   reset = 1;
   for(i=0;i<4;i=i+1) begin
      mcu_tick();
   end
   reset = 0;

   bclk = 1;
   while (~test_ready) begin
      mcu_tick();
   end

   for (i=0; i<10; i=i+1)
     begin
	test_ncs = 1;
	#tcyc bclk = 0;
	test_ncs = 0;
	#tcyc bclk = 1;
     end
   

   mcu_write(24'h123456, 16'habcd, 3);
   mcu_tick();
   mcu_read (24'h123456, 16'hxxcd);

   for(i=0;i<64;i=i+2)
     mcu_write (i, i, 0);
   for(i=0;i<64;i=i+2)
     begin
	mcu_tick();
	mcu_read (i, i);
     end

   test_ncs = 1;

   mcu_tick();

   #400000
   $finish;
end

endmodule // djsdram_test