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Subject: Re: [geda-user] DRC Error when imported old PCB layouts
From: Stephen Ecob <stephen DOT ecob AT sioi DOT com DOT au>
To: geda-user AT delorie DOT com
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--047d7b6d95e659ea1804e51d6a50
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The bug also shows up in my build of PCB, last synced to git head in March.
I managed to reduce the offending snippet down to just two polys, one line
and one component:

# release: pcb 1.99z

# To read pcb files, the pcb version (or the git source date) must be >=
the file version
FileVersion[20091103]

PCB["" 790.00mil 903.00mil]

Grid[1.000000 0.0000 0.0000 1]
PolyArea[3100.006200]
Thermal[0.500000]
DRC[7.49mil 0.10mil 8.00mil 8.00mil 15.00mil 8.00mil]
Flags("showdrc,rubberband,nameonpcb,autodrc,clearnew,snappin")
Groups("1,c:2,s:3")
Styles["Signal,12.00mil,38.00mil,20.00mil,10.00mil:Power,25.00mil,65.00mil,46.00mil,10.00mil:Fat,50.00mil,75.00mil,52.00mil,10.00mil:Skinny,9.00mil,32.00mil,16.00mil,10.00mil"]

Attribute("PCB::grid::unit" "mm")
Attribute("PCB::grid::size" "0.01mil")

Element["" "0603" "C1" "1u" 275.00mil 175.00mil -110.11mil -2.6510mm 0 100
""]
(
Pad[0.0000 31.49mil 0.0000 35.43mil 39.37mil 20.00mil 1.2540mm "input" "1"
"square,edge2"]
Pad[0.0000 -35.43mil 0.0000 -31.49mil 39.37mil 20.00mil 1.2540mm "input"
"2" "square"]
 ElementLine [34.68mil -70.11mil 34.68mil 70.11mil 10.00mil]
ElementLine [-34.68mil -70.11mil 34.68mil -70.11mil 10.00mil]
 ElementLine [-34.68mil -70.11mil -34.68mil 70.11mil 10.00mil]
ElementLine [-34.68mil 70.11mil 34.68mil 70.11mil 10.00mil]

)
Layer(1 "component")
(
Line[263.51mil 155.00mil 245.00mil 155.00mil 12.00mil 20.00mil ""]
 Polygon("clearpoly")
(
[255.00mil 260.00mil] [255.00mil 430.00mil] [340.00mil 430.00mil]
[340.00mil 260.00mil]
 )
Polygon("clearpoly")
(
[170.00mil 65.00mil] [170.00mil 405.00mil] [245.00mil 405.00mil] [245.00mil
110.00mil] [265.00mil 110.00mil]
 [265.00mil 65.00mil]
)
)
Layer(2 "solder")
(
)
Layer(9 "silk")
(
)
Layer(10 "silk")
(
)



On Fri, Aug 30, 2013 at 5:37 AM, John Luciani <jluciani AT gmail DOT com> wrote:

> I have a number of layouts made with the 20050315 version
> that I am trying to modify with the latest version of PCB (1.99z from git).
> Each layout I import has DRC clearance errors that are
> not visible on the screen. None of these errors occur in the 20050315
> version.
>
> The snippet below demonstrates this problem. Is there a filechange
> or setting change that is needed to import this old files?
>
> Thanks.
>
> (* jcl *)
>
>
> # release: pcb-bin 20050315
> # date:    Thu Aug 29 15:17:19 2013
> # user:    jluciani (jluciani,,,)
> # host:    paganini
>
> PCB["" 79000 90300]
>
> Grid[2500.00000000 0 0 1]
> Cursor[302590 77591 1.391741]
> Thermal[0.500000]
> DRC[749 10 800 800]
> Flags(0x00000000000018d8)
> Groups("1,c:2,s:3:4:5:6:7:8")
>
> Styles["Signal,1200,3800,2000,1000:Power,2500,6500,4600,1000:Fat,5000,7500,5200,1000:Skinny,900,3200,1600,1000"]
>
> Element[0x00000000 "SOT23-95P-280L1-5N__LTC_S5_Package" "U1" "unknown"
> 42500 17500 -5500 -13100 0 100 0x00000000]
> (
>     Pad[-6350 -3700 -3950 -3700 2400 2000 3400 "" "1" 0x00000100]
>     Pad[-6350 0 -3950 0 2400 2000 3400 "" "2" 0x00000100]
>     Pad[-6350 3700 -3950 3700 2400 2000 3400 "" "3" 0x00000100]
>     Pad[3950 3700 6350 3700 2400 2000 3400 "" "4" 0x00004100]
>     Pad[3950 -3700 6350 -3700 2400 2000 3400 "" "5" 0x00004100]
>     ElementLine [1750 2200 1750 6100 1000]
>     ElementLine [-1750 6100 1750 6100 1000]
>     ElementLine [-1750 2200 -1750 6100 1000]
>     ElementLine [1750 -6100 1750 -2200 1000]
>     ElementLine [-525 -6100 1750 -6100 1000]
>     ElementLine [-1750 -4875 -525 -6100 1000]
>     ElementLine [-1750 -4875 -1750 -2200 1000]
>
>     )
>
> Element[0x00000000 "0603" "C1" "1u" 27500 17500 -11011 -10437 0 100
> 0x00000000]
> (
>     Pad[0 3149 0 3543 3937 2000 4937 "input" "1" 0x00004100]
>     Pad[0 -3543 0 -3149 3937 2000 4937 "input" "2" 0x00000100]
>     ElementLine [3468 -7011 3468 7011 1000]
>     ElementLine [-3468 -7011 3468 -7011 1000]
>     ElementLine [-3468 -7011 -3468 7011 1000]
>     ElementLine [-3468 7011 3468 7011 1000]
>
>     )
> Layer(1 "component")
> (
>     Line[36150 21200 36000 21350 900 2000 0x00000020]
>     Line[26500 25000 26500 22500 1200 2000 0x00000000]
>     Line[31500 22000 29000 22000 1200 2000 0x00000000]
>     Line[27500 20649 28649 19500 1200 2000 0x00000000]
>     Line[32000 17500 36000 17500 1200 2000 0x00000000]
>     Line[27500 14351 26351 15500 1200 2000 0x00000000]
>     Line[26351 15500 24500 15500 1200 2000 0x00000000]
>     Line[28649 19500 31000 19500 1200 2000 0x00000000]
>     Line[36150 21200 36500 21550 900 2000 0x00000020]
>     Line[36150 21200 37000 22050 900 2000 0x00000020]
>     Polygon(0x00000000)
>     (
>         [25500 26000] [25500 43000] [34000 43000] [34000 26000]
>     )
>     Polygon(0x00000010)
>     (
>         [17000 6500] [17000 40500] [24500 40500] [24500 11000] [26500
> 11000]
>         [26500 6500]
>     )
>     Polygon(0x00000010)
>     (
>         [30500 16000] [30500 24000] [25500 24000] [25500 27000] [34000
> 27000]
>         [34000 16000]
>     )
> )
> Layer(2 "solder")
> (
> )
> Layer(3 "3")
> (
> )
> Layer(4 "4")
> (
> )
> Layer(5 "5")
> (
> )
> Layer(6 "6")
> (
> )
> Layer(7 "7")
> (
> )
> Layer(8 "8")
> (
> )
> Layer(9 "silk")
> (
> )
> Layer(10 "silk")
> (
> )
> NetList()
> (
>     Net("unnamed_net4" "(unknown)")
>     (
>         Connect("F1-2")
>         Connect("U2-1")
>         Connect("C4-1")
>     )
>     Net("unnamed_net3" "(unknown)")
>     (
>         Connect("S1-3")
>         Connect("D3-1")
>         Connect("D2-1")
>     )
>     Net("V_JACK" "(unknown)")
>     (
>         Connect("F1-1")
>         Connect("J1-3")
>     )
>     Net("V_BUS" "(unknown)")
>     (
>         Connect("S1-2")
>         Connect("J1-2")
>     )
>     Net("unnamed_net2" "(unknown)")
>     (
>         Connect("D1-2")
>         Connect("R1-2")
>     )
>     Net("VBAT" "(unknown)")
>     (
>         Connect("J2-1")
>         Connect("S1-1")
>         Connect("R1-1")
>         Connect("C2-2")
>         Connect("U1-5")
>     )
>     Net("+5V" "(unknown)")
>     (
>         Connect("D2-2")
>         Connect("C5-1")
>         Connect("U2-3")
>         Connect("U1-4")
>     )
>     Net("unnamed_net1" "(unknown)")
>     (
>         Connect("D1-1")
>         Connect("U1-3")
>     )
>     Net("GND" "(unknown)")
>     (
>         Connect("J2-2")
>         Connect("C5-2")
>         Connect("U2-4")
>         Connect("C4-2")
>         Connect("J1-5")
>         Connect("C2-1")
>         Connect("C1-1")
>         Connect("U1-2")
>     )
>     Net("V_USB" "(unknown)")
>     (
>         Connect("D3-2")
>         Connect("C1-2")
>         Connect("J1-1")
>         Connect("U1-1")
>     )
> )
>
>
>
>
>
>


-- 
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au

--047d7b6d95e659ea1804e51d6a50
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr">The bug also shows up in my build of PCB, last synced to g=
it head in March.<div>I managed to reduce the offending snippet down to jus=
t two polys, one line and one component:</div><div><br></div><div>
<div># release: pcb 1.99z</div><div><br></div><div># To read pcb files, the=
 pcb version (or the git source date) must be &gt;=3D the file version</div=
><div>FileVersion[20091103]</div><div><br></div><div>PCB[&quot;&quot; 790.0=
0mil 903.00mil]</div>

<div><br></div><div>Grid[1.000000 0.0000 0.0000 1]</div><div>PolyArea[3100.=
006200]</div><div>Thermal[0.500000]</div><div>DRC[7.49mil 0.10mil 8.00mil 8=
.00mil 15.00mil 8.00mil]</div><div>Flags(&quot;showdrc,rubberband,nameonpcb=
,autodrc,clearnew,snappin&quot;)</div>

<div>Groups(&quot;1,c:2,s:3&quot;)</div><div>Styles[&quot;Signal,12.00mil,3=
8.00mil,20.00mil,10.00mil:Power,25.00mil,65.00mil,46.00mil,10.00mil:Fat,50.=
00mil,75.00mil,52.00mil,10.00mil:Skinny,9.00mil,32.00mil,16.00mil,10.00mil&=
quot;]</div>

<div><br></div><div>Attribute(&quot;PCB::grid::unit&quot; &quot;mm&quot;)</=
div><div>Attribute(&quot;PCB::grid::size&quot; &quot;0.01mil&quot;)</div><d=
iv><br></div><div>Element[&quot;&quot; &quot;0603&quot; &quot;C1&quot; &quo=
t;1u&quot; 275.00mil 175.00mil -110.11mil -2.6510mm 0 100 &quot;&quot;]</di=
v>

<div>(</div><div><span style=3D"white-space:pre-wrap">	</span>Pad[0.0000 31=
.49mil 0.0000 35.43mil 39.37mil 20.00mil 1.2540mm &quot;input&quot; &quot;1=
&quot; &quot;square,edge2&quot;]</div><div><span style=3D"white-space:pre-w=
rap">	</span>Pad[0.0000 -35.43mil 0.0000 -31.49mil 39.37mil 20.00mil 1.2540=
mm &quot;input&quot; &quot;2&quot; &quot;square&quot;]</div>

<div><span style=3D"white-space:pre-wrap">	</span>ElementLine [34.68mil -70=
.11mil 34.68mil 70.11mil 10.00mil]</div><div><span style=3D"white-space:pre=
-wrap">	</span>ElementLine [-34.68mil -70.11mil 34.68mil -70.11mil 10.00mil=
]</div>

<div><span style=3D"white-space:pre-wrap">	</span>ElementLine [-34.68mil -7=
0.11mil -34.68mil 70.11mil 10.00mil]</div><div><span style=3D"white-space:p=
re-wrap">	</span>ElementLine [-34.68mil 70.11mil 34.68mil 70.11mil 10.00mil=
]</div>

<div><br></div><div><span style=3D"white-space:pre-wrap">	</span>)</div><di=
v>Layer(1 &quot;component&quot;)</div><div>(</div><div><span style=3D"white=
-space:pre-wrap">	</span>Line[263.51mil 155.00mil 245.00mil 155.00mil 12.00=
mil 20.00mil &quot;&quot;]</div>

<div><span style=3D"white-space:pre-wrap">	</span>Polygon(&quot;clearpoly&q=
uot;)</div><div><span style=3D"white-space:pre-wrap">	</span>(</div><div><s=
pan style=3D"white-space:pre-wrap">		</span>[255.00mil 260.00mil] [255.00mi=
l 430.00mil] [340.00mil 430.00mil] [340.00mil 260.00mil]=A0</div>

<div><span style=3D"white-space:pre-wrap">	</span>)</div><div><span style=
=3D"white-space:pre-wrap">	</span>Polygon(&quot;clearpoly&quot;)</div><div>=
<span style=3D"white-space:pre-wrap">	</span>(</div><div><span style=3D"whi=
te-space:pre-wrap">		</span>[170.00mil 65.00mil] [170.00mil 405.00mil] [245=
.00mil 405.00mil] [245.00mil 110.00mil] [265.00mil 110.00mil]=A0</div>

<div><span style=3D"white-space:pre-wrap">		</span>[265.00mil 65.00mil]=A0<=
/div><div><span style=3D"white-space:pre-wrap">	</span>)</div><div>)</div><=
div>Layer(2 &quot;solder&quot;)</div><div>(</div><div>)</div><div>Layer(9 &=
quot;silk&quot;)</div>

<div>(</div><div>)</div><div>Layer(10 &quot;silk&quot;)</div><div>(</div><d=
iv>)</div><div><br></div></div></div><div class=3D"gmail_extra"><br><br><di=
v class=3D"gmail_quote">On Fri, Aug 30, 2013 at 5:37 AM, John Luciani <span=
 dir=3D"ltr">&lt;<a href=3D"mailto:jluciani AT gmail DOT com" target=3D"_blank">jl=
uciani AT gmail DOT com</a>&gt;</span> wrote:<br>
<blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1p=
x #ccc solid;padding-left:1ex"><div dir=3D"ltr"><div><div><div><div><div>I =
have a number of layouts made with the 20050315 version<br>that I am trying=
 to modify with the latest version of PCB (1.99z from git).<br>
</div>Each layout I import has DRC clearance errors that are<br>
not visible on the screen. None of these errors occur in the 20050315<br>ve=
rsion.<br><br></div>The snippet below demonstrates this problem. Is there a=
 filechange<br></div>or setting change that is needed to import this old fi=
les?<br>

<br></div>Thanks.<br><br></div>(* jcl *)<br><br><br><div><div><div><div><di=
v><div><div># release: pcb-bin 20050315<br># date:=A0=A0=A0 Thu Aug 29 15:1=
7:19 2013<br># user:=A0=A0=A0 jluciani (jluciani,,,)<br># host:=A0=A0=A0 pa=
ganini<br><br>

PCB[&quot;&quot; 79000 90300]<br><br>Grid[2500.00000000 0 0 1]<br>Cursor[30=
2590 77591 1.391741]<br>Thermal[0.500000]<br>DRC[749 10 800 800]<br>Flags(0=
x00000000000018d8)<br>Groups(&quot;1,c:2,s:3:4:5:6:7:8&quot;)<br>Styles[&qu=
ot;Signal,1200,3800,2000,1000:Power,2500,6500,4600,1000:Fat,5000,7500,5200,=
1000:Skinny,900,3200,1600,1000&quot;]<br>

<br>Element[0x00000000 &quot;SOT23-95P-280L1-5N__LTC_S5_Package&quot; &quot=
;U1&quot; &quot;unknown&quot; 42500 17500 -5500 -13100 0 100 0x00000000]<br=
>(<br>=A0=A0=A0 Pad[-6350 -3700 -3950 -3700 2400 2000 3400 &quot;&quot; &qu=
ot;1&quot; 0x00000100]<br>

=A0=A0=A0 Pad[-6350 0 -3950 0 2400 2000 3400 &quot;&quot; &quot;2&quot; 0x0=
0000100]<br>=A0=A0=A0 Pad[-6350 3700 -3950 3700 2400 2000 3400 &quot;&quot;=
 &quot;3&quot; 0x00000100]<br>=A0=A0=A0 Pad[3950 3700 6350 3700 2400 2000 3=
400 &quot;&quot; &quot;4&quot; 0x00004100]<br>

=A0=A0=A0 Pad[3950 -3700 6350 -3700 2400 2000 3400 &quot;&quot; &quot;5&quo=
t; 0x00004100]<br>=A0=A0=A0 ElementLine [1750 2200 1750 6100 1000]<br>=A0=
=A0=A0 ElementLine [-1750 6100 1750 6100 1000]<br>=A0=A0=A0 ElementLine [-1=
750 2200 -1750 6100 1000]<br>

=A0=A0=A0 ElementLine [1750 -6100 1750 -2200 1000]<br>=A0=A0=A0 ElementLine=
 [-525 -6100 1750 -6100 1000]<br>=A0=A0=A0 ElementLine [-1750 -4875 -525 -6=
100 1000]<br>=A0=A0=A0 ElementLine [-1750 -4875 -1750 -2200 1000]<br><br>=
=A0=A0=A0 )<br><br>Element[0x00000000 &quot;0603&quot; &quot;C1&quot; &quot=
;1u&quot; 27500 17500 -11011 -10437 0 100 0x00000000]<br>

(<br>=A0=A0=A0 Pad[0 3149 0 3543 3937 2000 4937 &quot;input&quot; &quot;1&q=
uot; 0x00004100]<br>=A0=A0=A0 Pad[0 -3543 0 -3149 3937 2000 4937 &quot;inpu=
t&quot; &quot;2&quot; 0x00000100]<br>=A0=A0=A0 ElementLine [3468 -7011 3468=
 7011 1000]<br>

=A0=A0=A0 ElementLine [-3468 -7011 3468 -7011 1000]<br>=A0=A0=A0 ElementLin=
e [-3468 -7011 -3468 7011 1000]<br>=A0=A0=A0 ElementLine [-3468 7011 3468 7=
011 1000]<br><br>=A0=A0=A0 )<br>Layer(1 &quot;component&quot;)<br>(<br>=A0=
=A0=A0 Line[36150 21200 36000 21350 900 2000 0x00000020]<br>

=A0=A0=A0 Line[26500 25000 26500 22500 1200 2000 0x00000000]<br>=A0=A0=A0 L=
ine[31500 22000 29000 22000 1200 2000 0x00000000]<br>=A0=A0=A0 Line[27500 2=
0649 28649 19500 1200 2000 0x00000000]<br>=A0=A0=A0 Line[32000 17500 36000 =
17500 1200 2000 0x00000000]<br>

=A0=A0=A0 Line[27500 14351 26351 15500 1200 2000 0x00000000]<br>=A0=A0=A0 L=
ine[26351 15500 24500 15500 1200 2000 0x00000000]<br>=A0=A0=A0 Line[28649 1=
9500 31000 19500 1200 2000 0x00000000]<br>=A0=A0=A0 Line[36150 21200 36500 =
21550 900 2000 0x00000020]<br>

=A0=A0=A0 Line[36150 21200 37000 22050 900 2000 0x00000020]<br>=A0=A0=A0 Po=
lygon(0x00000000)<br>=A0=A0=A0 (<br>=A0=A0=A0 =A0=A0=A0 [25500 26000] [2550=
0 43000] [34000 43000] [34000 26000] <br>=A0=A0=A0 )<br>=A0=A0=A0 Polygon(0=
x00000010)<br>=A0=A0=A0 (<br>=A0=A0=A0 =A0=A0=A0 [17000 6500] [17000 40500]=
 [24500 40500] [24500 11000] [26500 11000] <br>

=A0=A0=A0 =A0=A0=A0 [26500 6500] <br>=A0=A0=A0 )<br>=A0=A0=A0 Polygon(0x000=
00010)<br>=A0=A0=A0 (<br>=A0=A0=A0 =A0=A0=A0 [30500 16000] [30500 24000] [2=
5500 24000] [25500 27000] [34000 27000] <br>=A0=A0=A0 =A0=A0=A0 [34000 1600=
0] <br>=A0=A0=A0 )<br>)<br>Layer(2 &quot;solder&quot;)<br>

(<br>)<br>Layer(3 &quot;3&quot;)<br>(<br>)<br>Layer(4 &quot;4&quot;)<br>(<b=
r>)<br>Layer(5 &quot;5&quot;)<br>(<br>)<br>Layer(6 &quot;6&quot;)<br>(<br>)=
<br>Layer(7 &quot;7&quot;)<br>(<br>)<br>Layer(8 &quot;8&quot;)<br>(<br>

)<br>Layer(9 &quot;silk&quot;)<br>(<br>)<br>Layer(10 &quot;silk&quot;)<br>(=
<br>)<br>NetList()<br>(<br>=A0=A0=A0 Net(&quot;unnamed_net4&quot; &quot;(un=
known)&quot;)<br>=A0=A0=A0 (<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;F1-2&quot=
;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;U2-1&quot;)<br>

=A0=A0=A0 =A0=A0=A0 Connect(&quot;C4-1&quot;)<br>=A0=A0=A0 )<br>=A0=A0=A0 N=
et(&quot;unnamed_net3&quot; &quot;(unknown)&quot;)<br>=A0=A0=A0 (<br>=A0=A0=
=A0 =A0=A0=A0 Connect(&quot;S1-3&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quo=
t;D3-1&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;D2-1&quot;)<br>

=A0=A0=A0 )<br>=A0=A0=A0 Net(&quot;V_JACK&quot; &quot;(unknown)&quot;)<br>=
=A0=A0=A0 (<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;F1-1&quot;)<br>=A0=A0=A0 =
=A0=A0=A0 Connect(&quot;J1-3&quot;)<br>=A0=A0=A0 )<br>=A0=A0=A0 Net(&quot;V=
_BUS&quot; &quot;(unknown)&quot;)<br>=A0=A0=A0 (<br>=A0=A0=A0 =A0=A0=A0 Con=
nect(&quot;S1-2&quot;)<br>

=A0=A0=A0 =A0=A0=A0 Connect(&quot;J1-2&quot;)<br>=A0=A0=A0 )<br>=A0=A0=A0 N=
et(&quot;unnamed_net2&quot; &quot;(unknown)&quot;)<br>=A0=A0=A0 (<br>=A0=A0=
=A0 =A0=A0=A0 Connect(&quot;D1-2&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quo=
t;R1-2&quot;)<br>=A0=A0=A0 )<br>=A0=A0=A0 Net(&quot;VBAT&quot; &quot;(unkno=
wn)&quot;)<br>

=A0=A0=A0 (<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;J2-1&quot;)<br>=A0=A0=A0 =
=A0=A0=A0 Connect(&quot;S1-1&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;R1=
-1&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;C2-2&quot;)<br>=A0=A0=A0 =A0=
=A0=A0 Connect(&quot;U1-5&quot;)<br>=A0=A0=A0 )<br>=A0=A0=A0 Net(&quot;+5V&=
quot; &quot;(unknown)&quot;)<br>

=A0=A0=A0 (<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;D2-2&quot;)<br>=A0=A0=A0 =
=A0=A0=A0 Connect(&quot;C5-1&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;U2=
-3&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;U1-4&quot;)<br>=A0=A0=A0 )<b=
r>=A0=A0=A0 Net(&quot;unnamed_net1&quot; &quot;(unknown)&quot;)<br>

=A0=A0=A0 (<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;D1-1&quot;)<br>=A0=A0=A0 =
=A0=A0=A0 Connect(&quot;U1-3&quot;)<br>=A0=A0=A0 )<br>=A0=A0=A0 Net(&quot;G=
ND&quot; &quot;(unknown)&quot;)<br>=A0=A0=A0 (<br>=A0=A0=A0 =A0=A0=A0 Conne=
ct(&quot;J2-2&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;C5-2&quot;)<br>

=A0=A0=A0 =A0=A0=A0 Connect(&quot;U2-4&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connec=
t(&quot;C4-2&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;J1-5&quot;)<br>=A0=
=A0=A0 =A0=A0=A0 Connect(&quot;C2-1&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&=
quot;C1-1&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;U1-2&quot;)<br>

=A0=A0=A0 )<br>=A0=A0=A0 Net(&quot;V_USB&quot; &quot;(unknown)&quot;)<br>=
=A0=A0=A0 (<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;D3-2&quot;)<br>=A0=A0=A0 =
=A0=A0=A0 Connect(&quot;C1-2&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;J1=
-1&quot;)<br>=A0=A0=A0 =A0=A0=A0 Connect(&quot;U1-1&quot;)<br>=A0=A0=A0 )<b=
r>

)<br><br><br><br><br clear=3D"all"><br></div></div></div></div></div></div>=
</div></div>
</blockquote></div><br><br clear=3D"all"><div><br></div>-- <br>Stephen Ecob=
<br>Silicon On Inspiration<br>Sydney Australia<br><a href=3D"http://www.sio=
i.com.au" target=3D"_blank">www.sioi.com.au</a><br>
</div>

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