X-Authentication-Warning: delorie.com: mail set sender to geda-user-bounces using -f X-Recipient: geda-user AT delorie DOT com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:content-type :content-transfer-encoding; bh=3eGE2hbxmgumJ+gSDGBrCWUIB03sHzS8iti6cQsmXlA=; b=wvwi8J1pGhP/dl+BjjrElHTQOjlL2qQjX8aVNFdK+2DeJ/Mqv2tBTsrSt7DZmaiMiL T7cdLukSDRrulXXGCz/C2pscQKevOlw5WhAB2azpqncDzktldqJQ9U3QLNY3Y2kN0bSB LJQYPfdO1/poJzW55AhJSnRPqiMb+n+akUx7c= MIME-Version: 1.0 Sender: silicon DOT on DOT inspiration AT gmail DOT com In-Reply-To: <20111117204524.10e586f5@rainbird> References: <20111117204524 DOT 10e586f5 AT rainbird> Date: Sat, 19 Nov 2011 08:15:35 +1100 X-Google-Sender-Auth: 3WPM5NMbc6lNBEAnlP_SO3RKYIc Message-ID: Subject: Re: [geda-user] Modern GAL/PAL design with gEDA? From: Stephen Ecob To: geda-user AT delorie DOT com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by delorie.com id pAILFei6023647 Reply-To: geda-user AT delorie DOT com Errors-To: nobody AT delorie DOT com X-Mailing-List: geda-user AT delorie DOT com X-Unsubscribes-To: listserv AT delorie DOT com Precedence: bulk On Fri, Nov 18, 2011 at 12:45 PM, Vanessa Ezekowitz wrote: > > When it comes to making circuit boards out of chips and discrete components, I'm reasonably well educated, and gschem -> pcb is a no-brainer for me these days.  Similarly, I'm no stranger to programming, though I prefer to direct my efforts at vintage computing. Still, I think I've gotten pretty good at both concepts.  :-) > > However, my latest project requires something I've never even begun to touch before:  Programmable logic devices. > > So, here's what I want to do: > > I've drawn a small circuit in gschem consisting of four flip-flops and a handful of gates.  It isn't complete yet, but what I have seems to work exactly the way I want, and there's enough here to build a physical circuit to test the design's core function.  Each symbol has a refdes, none have been assigned footprints or slots (since neither seems like it would make sense in this case). > > Now I need to translate that schematic into something (a JEDEC file?) that I can burn into a 22V10 GAL.  I realize this is an older type of chip, but they are easy to purchase from Digikey and the like, and my current project only calls for enough logic to fill one of these - a CPLD or FPGA is just plain overkill. For a more modern approach to tiny programmable logic take a look at the Silego GreenPak. GreenPak1 may be too small for your circuit, but GreenPak2 may be a good fit: http://www.silego.com/index.php?page=greenpak2 It's an interesting and versatile approach to tiny programmable logic.