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Date: Fri, 7 Jul 2017 22:50:59 +0300
From: "Vladimir Zhbanov (vzhbanov AT gmail DOT com) [via geda-user AT delorie DOT com]" <geda-user AT delorie DOT com>
To: geda-user AT delorie DOT com
Subject: Re: [geda-user] Refdes= mangling
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On Thu, Jul 06, 2017 at 05:14:16PM +0200, Nicklas Karlsson (nicklas DOT karlsson17 AT gmail DOT com) [via geda-user AT delorie DOT com] wrote:
> > Hi, fellow gEDA users,
> > 
> > ...
> > 
> > Now, one of my ideas is to move mangling of hierarchy related
> > attributes to the post-processing stage in order to process schematic
> > pages and subpages separately, creating isolated subcircuits first.
> 
> Sounds reasonable, only problem with name hierarchical name is they get to long to fit on circuit board.
> 
> > After some time of thinking, I realise the use cases when net= is
> > mangled or not. The former case is for subcircuits that share their
> > power sources, the latter is for such cases where such power sources
> > are would-be-isolated within the subschematics.
> 
> If alias is possible I think it is a good idea to use for old or new name?
> 
> > Are there use cases where it is OK to use refdes= without mangling in
> > flattened hierarchical schematic netlist? I see only a field for
> > various potential conflicts...
> > 
> > Thank you,
> >   Vladimir
> > 
> > [1] https://github.com/lepton-eda/lepton-eda/pull/139
> 
> 
> Not related but I think there is a problem with lowercase letters in gnetlist and maybe space for net names then, at least then using them in pcb they do now show up in list of known nets.

Nicklas, thank you for your points! They (together with your
previous post and reading Roland's code) gave me the idea that 'no
refdes mangling' might be useful for re-using parts of previously
created schematics. Though the user has to make provisions against
possible conflicts with existing refdeses.

-- 
  Vladimir